| Line 118... |
Line 118... |
signal shift_funcD : shift_function_type;
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signal shift_funcD : shift_function_type;
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signal mult_func : mult_function_type;
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signal mult_func : mult_function_type;
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signal mult_funcD : mult_function_type;
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signal mult_funcD : mult_function_type;
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signal branch_func : branch_function_type;
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signal branch_func : branch_function_type;
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signal take_branch : std_logic;
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signal take_branch : std_logic;
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signal take_branchD : std_logic;
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signal a_source : a_source_type;
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signal a_source : a_source_type;
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signal b_source : b_source_type;
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signal b_source : b_source_type;
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signal c_source : c_source_type;
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signal c_source : c_source_type;
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signal pc_source : pc_source_type;
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signal pc_source : pc_source_type;
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signal mem_source : mem_source_type;
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signal mem_source : mem_source_type;
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| Line 140... |
Line 139... |
begin --architecture
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begin --architecture
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|
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pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
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pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
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pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
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pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
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pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
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pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
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nullify_op <= '1' when pc_source = from_lbranch and take_branchD = '0' else
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nullify_op <= '1' when pc_source = from_lbranch and take_branch = '0' else '0';
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'0';
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c_bus <= c_alu or c_shift or c_mult;
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c_bus <= c_alu or c_shift or c_mult;
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reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
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reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
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|
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--synchronize reset and interrupt pins
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--synchronize reset and interrupt pins
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intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
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intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
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| Line 172... |
Line 170... |
end process;
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end process;
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|
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u1_pc_next: pc_next PORT MAP (
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u1_pc_next: pc_next PORT MAP (
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clk => clk,
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clk => clk,
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reset_in => reset,
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reset_in => reset,
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take_branch => take_branchD,
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take_branch => take_branch,
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pause_in => pause_any,
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pause_in => pause_any,
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pc_new => c_bus(31 downto 2),
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pc_new => c_bus(31 downto 2),
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opcode25_0 => opcode(25 downto 0),
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opcode25_0 => opcode(25 downto 0),
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pc_source => pc_source,
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pc_source => pc_source,
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pc_out => pc,
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pc_out => pc,
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| Line 286... |
Line 284... |
shift_funcD <= shift_func;
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shift_funcD <= shift_func;
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mult_funcD <= mult_func;
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mult_funcD <= mult_func;
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rd_indexD <= rd_index;
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rd_indexD <= rd_index;
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|
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reg_destD <= reg_dest;
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reg_destD <= reg_dest;
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take_branchD <= take_branch;
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pause_pipeline <= '0';
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pause_pipeline <= '0';
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end generate; --pipeline2
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end generate; --pipeline2
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|
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pipeline3: if pipeline_stages >= 3 generate
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pipeline3: if pipeline_stages >= 3 generate
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--When operating in three stage pipeline mode, the following signals
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--When operating in three stage pipeline mode, the following signals
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| Line 320... |
Line 317... |
mem_source => mem_source,
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mem_source => mem_source,
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a_source => a_source,
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a_source => a_source,
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b_source => b_source,
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b_source => b_source,
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c_source => c_source,
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c_source => c_source,
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c_bus => c_bus,
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c_bus => c_bus,
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take_branch => take_branch,
|
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take_branchD => take_branchD,
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pause_any => pause_any,
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pause_any => pause_any,
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pause_pipeline => pause_pipeline);
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pause_pipeline => pause_pipeline);
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end generate; --pipeline3
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end generate; --pipeline3
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|
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end; --architecture logic
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end; --architecture logic
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