| Line 83... |
Line 83... |
constant BRANCH_EQ : branch_function_type := "010";
|
constant BRANCH_EQ : branch_function_type := "010";
|
constant BRANCH_NE : branch_function_type := "011";
|
constant BRANCH_NE : branch_function_type := "011";
|
constant BRANCH_GEZ : branch_function_type := "100";
|
constant BRANCH_GEZ : branch_function_type := "100";
|
constant BRANCH_GTZ : branch_function_type := "101";
|
constant BRANCH_GTZ : branch_function_type := "101";
|
constant BRANCH_YES : branch_function_type := "110";
|
constant BRANCH_YES : branch_function_type := "110";
|
|
constant BRANCH_NO : branch_function_type := "111";
|
|
|
-- mode(32=1,16=2,8=3), signed, write
|
-- mode(32=1,16=2,8=3), signed, write
|
subtype mem_source_type is std_logic_vector(3 downto 0);
|
subtype mem_source_type is std_logic_vector(3 downto 0);
|
constant MEM_FETCH : mem_source_type := "0000";
|
constant MEM_FETCH : mem_source_type := "0000";
|
constant MEM_READ32 : mem_source_type := "0100";
|
constant MEM_READ32 : mem_source_type := "0100";
|
constant MEM_WRITE32 : mem_source_type := "0101";
|
constant MEM_WRITE32 : mem_source_type := "0101";
|
constant MEM_READ16 : mem_source_type := "1000";
|
constant MEM_READ16 : mem_source_type := "1000";
|
constant MEM_READ16s : mem_source_type := "1010";
|
constant MEM_READ16S : mem_source_type := "1010";
|
constant MEM_WRITE16 : mem_source_type := "1001";
|
constant MEM_WRITE16 : mem_source_type := "1001";
|
constant MEM_READ8 : mem_source_type := "1100";
|
constant MEM_READ8 : mem_source_type := "1100";
|
constant MEM_READ8s : mem_source_type := "1110";
|
constant MEM_READ8S : mem_source_type := "1110";
|
constant MEM_WRITE8 : mem_source_type := "1101";
|
constant MEM_WRITE8 : mem_source_type := "1101";
|
|
|
function bv_to_integer(bv: in std_logic_vector) return integer;
|
function bv_adder(a : in std_logic_vector;
|
function bv_adder(a : in std_logic_vector(32 downto 0);
|
b : in std_logic_vector;
|
b : in std_logic_vector(32 downto 0);
|
|
do_add: in std_logic) return std_logic_vector;
|
|
function bv_adder_lookahead(
|
|
a : in std_logic_vector(32 downto 0);
|
|
b : in std_logic_vector(32 downto 0);
|
|
do_add: in std_logic) return std_logic_vector;
|
do_add: in std_logic) return std_logic_vector;
|
function bv_negate(a : in std_logic_vector) return std_logic_vector;
|
function bv_negate(a : in std_logic_vector) return std_logic_vector;
|
function bv_increment(a : in std_logic_vector(31 downto 2)
|
function bv_increment(a : in std_logic_vector(31 downto 2)
|
) return std_logic_vector;
|
) return std_logic_vector;
|
function bv_inc6(a : in std_logic_vector
|
function bv_inc(a : in std_logic_vector
|
) return std_logic_vector;
|
) return std_logic_vector;
|
|
|
-- For Altera
|
-- For Altera
|
COMPONENT lpm_add_sub
|
COMPONENT lpm_add_sub
|
GENERIC (
|
GENERIC (
|
| Line 220... |
Line 216... |
pc_new : in std_logic_vector(31 downto 2);
|
pc_new : in std_logic_vector(31 downto 2);
|
take_branch : in std_logic;
|
take_branch : in std_logic;
|
pause_in : in std_logic;
|
pause_in : in std_logic;
|
opcode25_0 : in std_logic_vector(25 downto 0);
|
opcode25_0 : in std_logic_vector(25 downto 0);
|
pc_source : in pc_source_type;
|
pc_source : in pc_source_type;
|
pc_out : out std_logic_vector(31 downto 0);
|
pc_future : out std_logic_vector(31 downto 2);
|
pc_out_plus4 : out std_logic_vector(31 downto 0));
|
pc_current : out std_logic_vector(31 downto 2);
|
|
pc_plus4 : out std_logic_vector(31 downto 2));
|
end component;
|
end component;
|
|
|
component mem_ctrl
|
component mem_ctrl
|
generic(ACCURATE_TIMING : boolean := false);
|
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
pause_in : in std_logic;
|
pause_in : in std_logic;
|
nullify_op : in std_logic;
|
nullify_op : in std_logic;
|
address_pc : in std_logic_vector(31 downto 0);
|
address_pc : in std_logic_vector(31 downto 2);
|
opcode_out : out std_logic_vector(31 downto 0);
|
opcode_out : out std_logic_vector(31 downto 0);
|
|
|
address_data : in std_logic_vector(31 downto 0);
|
address_in : in std_logic_vector(31 downto 0);
|
mem_source : in mem_source_type;
|
mem_source : in mem_source_type;
|
data_write : in std_logic_vector(31 downto 0);
|
data_write : in std_logic_vector(31 downto 0);
|
data_read : out std_logic_vector(31 downto 0);
|
data_read : out std_logic_vector(31 downto 0);
|
pause_out : out std_logic;
|
pause_out : out std_logic;
|
|
|
mem_address : out std_logic_vector(31 downto 0);
|
mem_address : out std_logic_vector(31 downto 2);
|
mem_data_w : out std_logic_vector(31 downto 0);
|
mem_data_w : out std_logic_vector(31 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
mem_byte_sel : out std_logic_vector(3 downto 0);
|
mem_byte_we : out std_logic_vector(3 downto 0));
|
mem_write : out std_logic);
|
|
end component;
|
end component;
|
|
|
component control
|
component control
|
port(opcode : in std_logic_vector(31 downto 0);
|
port(opcode : in std_logic_vector(31 downto 0);
|
intr_signal : in std_logic;
|
intr_signal : in std_logic;
|
| Line 265... |
Line 260... |
pc_source_out: out pc_source_type;
|
pc_source_out: out pc_source_type;
|
mem_source_out:out mem_source_type);
|
mem_source_out:out mem_source_type);
|
end component;
|
end component;
|
|
|
component reg_bank
|
component reg_bank
|
generic(memory_type : string := "TRI_PORT");
|
generic(memory_type : string := "XILINX_16X");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
pause : in std_logic;
|
pause : in std_logic;
|
rs_index : in std_logic_vector(5 downto 0);
|
rs_index : in std_logic_vector(5 downto 0);
|
rt_index : in std_logic_vector(5 downto 0);
|
rt_index : in std_logic_vector(5 downto 0);
|
| Line 290... |
Line 285... |
b_mux : in b_source_type;
|
b_mux : in b_source_type;
|
b_out : out std_logic_vector(31 downto 0);
|
b_out : out std_logic_vector(31 downto 0);
|
|
|
c_bus : in std_logic_vector(31 downto 0);
|
c_bus : in std_logic_vector(31 downto 0);
|
c_memory : in std_logic_vector(31 downto 0);
|
c_memory : in std_logic_vector(31 downto 0);
|
c_pc : in std_logic_vector(31 downto 0);
|
c_pc : in std_logic_vector(31 downto 2);
|
c_pc_plus4 : in std_logic_vector(31 downto 0);
|
c_pc_plus4 : in std_logic_vector(31 downto 2);
|
c_mux : in c_source_type;
|
c_mux : in c_source_type;
|
reg_dest_out : out std_logic_vector(31 downto 0);
|
reg_dest_out : out std_logic_vector(31 downto 0);
|
|
|
branch_func : in branch_function_type;
|
branch_func : in branch_function_type;
|
take_branch : out std_logic);
|
take_branch : out std_logic);
|
end component;
|
end component;
|
|
|
component alu
|
component alu
|
generic(adder_type : string := "DEFAULT";
|
generic(alu_type : string := "DEFAULT");
|
alu_type : string := "DEFAULT");
|
|
port(a_in : in std_logic_vector(31 downto 0);
|
port(a_in : in std_logic_vector(31 downto 0);
|
b_in : in std_logic_vector(31 downto 0);
|
b_in : in std_logic_vector(31 downto 0);
|
alu_function : in alu_function_type;
|
alu_function : in alu_function_type;
|
c_alu : out std_logic_vector(31 downto 0));
|
c_alu : out std_logic_vector(31 downto 0));
|
end component;
|
end component;
|
| Line 317... |
Line 311... |
shift_func : in shift_function_type;
|
shift_func : in shift_function_type;
|
c_shift : out std_logic_vector(31 downto 0));
|
c_shift : out std_logic_vector(31 downto 0));
|
end component;
|
end component;
|
|
|
component mult
|
component mult
|
generic (
|
generic(mult_type : string := "DEFAULT");
|
adder_type : string := "DEFAULT";
|
port(clk : in std_logic;
|
mult_type : string := "DEFAULT");
|
|
port (
|
|
clk : in std_logic;
|
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
a, b : in std_logic_vector(31 downto 0);
|
a, b : in std_logic_vector(31 downto 0);
|
mult_func : in mult_function_type;
|
mult_func : in mult_function_type;
|
c_mult : out std_logic_vector(31 downto 0);
|
c_mult : out std_logic_vector(31 downto 0);
|
pause_out : out std_logic);
|
pause_out : out std_logic);
|
| Line 360... |
Line 351... |
pause_any : in std_logic;
|
pause_any : in std_logic;
|
pause_pipeline : out std_logic);
|
pause_pipeline : out std_logic);
|
end component;
|
end component;
|
|
|
component mlite_cpu
|
component mlite_cpu
|
generic(memory_type : string := "ALTERA";
|
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
|
mult_type : string := "DEFAULT";
|
mult_type : string := "DEFAULT";
|
shifter_type : string := "DEFAULT";
|
shifter_type : string := "DEFAULT";
|
pipeline_stages : natural := 3);
|
alu_type : string := "DEFAULT";
|
|
pipeline_stages : natural := 3); --3 or 4
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
intr_in : in std_logic;
|
intr_in : in std_logic;
|
|
|
mem_address : out std_logic_vector(31 downto 0);
|
mem_address : out std_logic_vector(31 downto 0);
|
mem_data_w : out std_logic_vector(31 downto 0);
|
mem_data_w : out std_logic_vector(31 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
mem_byte_sel: out std_logic_vector(3 downto 0);
|
mem_byte_we : out std_logic_vector(3 downto 0);
|
mem_write : out std_logic;
|
|
mem_pause : in std_logic);
|
mem_pause : in std_logic);
|
end component;
|
end component;
|
|
|
component ram
|
component ram
|
generic(memory_type : string := "DEFAULT");
|
generic(memory_type : string := "DEFAULT");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
mem_byte_sel : in std_logic_vector(3 downto 0);
|
enable : in std_logic;
|
mem_write : in std_logic;
|
write_byte_enable : in std_logic_vector(3 downto 0);
|
mem_address : in std_logic_vector(31 downto 0);
|
address : in std_logic_vector(31 downto 2);
|
mem_data_w : in std_logic_vector(31 downto 0);
|
data_write : in std_logic_vector(31 downto 0);
|
mem_data_r : out std_logic_vector(31 downto 0));
|
data_read : out std_logic_vector(31 downto 0));
|
end component; --ram
|
end component; --ram
|
|
|
component uart
|
component uart
|
generic(log_file : string := "UNUSED");
|
generic(log_file : string := "UNUSED");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
uart_sel : in std_logic;
|
enable_read : in std_logic;
|
data : in std_logic_vector(7 downto 0);
|
enable_write : in std_logic;
|
|
data_in : in std_logic_vector(7 downto 0);
|
|
data_out : out std_logic_vector(7 downto 0);
|
uart_read : in std_logic;
|
uart_read : in std_logic;
|
uart_write : out std_logic;
|
uart_write : out std_logic;
|
pause : out std_logic);
|
busy_write : out std_logic;
|
|
data_avail : out std_logic);
|
end component; --uart
|
end component; --uart
|
|
|
component plasma
|
component plasma
|
generic(memory_type : string := "DEFAULT";
|
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
|
log_file : string := "UNUSED");
|
log_file : string := "UNUSED");
|
port(clk_in : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset : in std_logic;
|
intr_in : in std_logic;
|
|
|
|
uart_read : in std_logic;
|
|
uart_write : out std_logic;
|
uart_write : out std_logic;
|
|
|
mem_address_out : out std_logic_vector(31 downto 0);
|
|
mem_data : out std_logic_vector(31 downto 0);
|
|
mem_byte_sel_out : out std_logic_vector(3 downto 0);
|
|
mem_write_out : out std_logic;
|
|
mem_pause_in : in std_logic);
|
|
end component; --plasma
|
|
|
|
component plasma_if
|
|
generic(memory_type : string := "ALTERA";
|
|
log_file : string := "UNUSED");
|
|
port(clk_in : in std_logic;
|
|
reset_n : in std_logic;
|
|
uart_read : in std_logic;
|
uart_read : in std_logic;
|
uart_write : out std_logic;
|
|
|
|
address : out std_logic_vector(31 downto 0);
|
address : out std_logic_vector(31 downto 2);
|
data : out std_logic_vector(31 downto 0);
|
data_write : out std_logic_vector(31 downto 0);
|
we_n : out std_logic;
|
data_read : in std_logic_vector(31 downto 0);
|
oe_n : out std_logic;
|
write_byte_enable : out std_logic_vector(3 downto 0);
|
be_n : out std_logic_vector(3 downto 0);
|
mem_pause_in : in std_logic;
|
sram0_cs_n : out std_logic;
|
|
sram1_cs_n : out std_logic);
|
|
end component; --plasma_if
|
|
|
|
end; --package mlite_pack
|
gpio0_out : out std_logic_vector(31 downto 0);
|
|
gpioA_in : in std_logic_vector(31 downto 0));
|
|
end component; --plasma
|
|
|
package body mlite_pack is
|
end; --package mlite_pack
|
|
|
function bv_to_integer(bv: in std_logic_vector) return integer is
|
|
variable result : integer;
|
|
variable b : integer;
|
|
begin
|
|
result := 0;
|
|
b := 0;
|
|
for index in bv'range loop
|
|
if bv(index) = '1' then
|
|
b := 1;
|
|
else
|
|
b := 0;
|
|
end if;
|
|
result := result * 2 + b;
|
|
end loop;
|
|
return result;
|
|
end; --function bv_to_integer
|
|
|
|
|
package body mlite_pack is
|
|
|
function bv_adder(a : in std_logic_vector(32 downto 0);
|
function bv_adder(a : in std_logic_vector;
|
b : in std_logic_vector(32 downto 0);
|
b : in std_logic_vector;
|
do_add: in std_logic) return std_logic_vector is
|
do_add: in std_logic) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable bb : std_logic_vector(32 downto 0);
|
variable bb : std_logic_vector(a'length-1 downto 0);
|
variable result : std_logic_vector(32 downto 0);
|
variable result : std_logic_vector(a'length downto 0);
|
begin
|
begin
|
result := '0' & ZERO;
|
|
if do_add = '1' then
|
if do_add = '1' then
|
bb := b;
|
bb := b;
|
carry_in := '0';
|
carry_in := '0';
|
else
|
else
|
bb := not b;
|
bb := not b;
|
carry_in := '1';
|
carry_in := '1';
|
end if;
|
end if;
|
for index in 0 to 32 loop
|
for index in 0 to a'length-1 loop
|
result(index) := a(index) xor bb(index) xor carry_in;
|
result(index) := a(index) xor bb(index) xor carry_in;
|
carry_in := (carry_in and (a(index) or bb(index))) or
|
carry_in := (carry_in and (a(index) or bb(index))) or
|
(a(index) and bb(index));
|
(a(index) and bb(index));
|
end loop;
|
end loop;
|
return result;
|
result(a'length) := carry_in xnor do_add;
|
end; --function
|
|
|
|
|
|
function bv_adder_lookahead(
|
|
a : in std_logic_vector(32 downto 0);
|
|
b : in std_logic_vector(32 downto 0);
|
|
do_add: in std_logic) return std_logic_vector is
|
|
variable carry : std_logic_vector(32 downto 0);
|
|
variable p, g : std_logic_vector(32 downto 0);
|
|
variable bb : std_logic_vector(32 downto 0);
|
|
variable result : std_logic_vector(32 downto 0);
|
|
variable i : natural;
|
|
begin
|
|
carry := '0' & ZERO;
|
|
if do_add = '1' then
|
|
bb := b;
|
|
carry(0) := '0';
|
|
else
|
|
bb := not b;
|
|
carry(0) := '1';
|
|
end if;
|
|
|
|
p := a or bb; --propogate
|
|
g := a and bb; --generate
|
|
for index in 0 to 7 loop
|
|
i := index*4;
|
|
carry(i+1) := g(i) or
|
|
(p(i) and carry(i));
|
|
i := index*4+1;
|
|
carry(i+1) := g(i) or
|
|
(p(i) and g(i-1)) or
|
|
((p(i) and p(i-1)) and carry(i-1));
|
|
i := index*4+2;
|
|
carry(i+1) := g(i) or
|
|
(p(i) and g(i-1)) or
|
|
(p(i) and p(i-1) and g(i-2)) or
|
|
((p(i) and p(i-1) and p(i-2)) and carry(i-2));
|
|
i := index*4+3;
|
|
carry(i+1) := g(i) or
|
|
(p(i) and g(i-1)) or
|
|
(p(i) and p(i-1) and g(i-2)) or
|
|
(p(i) and p(i-1) and p(i-2) and g(i-3)) or
|
|
(((p(i) and p(i-1)) and (p(i-2) and p(i-3)))
|
|
and carry(i-3));
|
|
end loop;
|
|
result := (a xor bb) xor carry;
|
|
return result;
|
return result;
|
end; --function
|
end; --function
|
|
|
|
|
function bv_negate(a : in std_logic_vector) return std_logic_vector is
|
function bv_negate(a : in std_logic_vector) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable not_a : std_logic_vector(31 downto 0);
|
variable not_a : std_logic_vector(a'length-1 downto 0);
|
variable result : std_logic_vector(31 downto 0);
|
variable result : std_logic_vector(a'length-1 downto 0);
|
begin
|
begin
|
result := ZERO;
|
|
not_a := not a;
|
not_a := not a;
|
carry_in := '1';
|
carry_in := '1';
|
for index in a'reverse_range loop
|
for index in a'reverse_range loop
|
result(index) := not_a(index) xor carry_in;
|
result(index) := not_a(index) xor carry_in;
|
carry_in := carry_in and not_a(index);
|
carry_in := carry_in and not_a(index);
|
| Line 545... |
Line 458... |
function bv_increment(a : in std_logic_vector(31 downto 2)
|
function bv_increment(a : in std_logic_vector(31 downto 2)
|
) return std_logic_vector is
|
) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable result : std_logic_vector(31 downto 2);
|
variable result : std_logic_vector(31 downto 2);
|
begin
|
begin
|
result := ZERO(31 downto 2);
|
|
carry_in := '1';
|
carry_in := '1';
|
for index in 2 to 31 loop
|
for index in 2 to 31 loop
|
result(index) := a(index) xor carry_in;
|
result(index) := a(index) xor carry_in;
|
carry_in := a(index) and carry_in;
|
carry_in := a(index) and carry_in;
|
end loop;
|
end loop;
|
return result;
|
return result;
|
end; --function
|
end; --function
|
|
|
|
|
function bv_inc6(a : in std_logic_vector
|
function bv_inc(a : in std_logic_vector
|
) return std_logic_vector is
|
) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable result : std_logic_vector(5 downto 0);
|
variable result : std_logic_vector(a'length-1 downto 0);
|
begin
|
begin
|
result := "000000";
|
|
carry_in := '1';
|
carry_in := '1';
|
for index in 0 to 5 loop
|
for index in 0 to a'length-1 loop
|
result(index) := a(index) xor carry_in;
|
result(index) := a(index) xor carry_in;
|
carry_in := a(index) and carry_in;
|
carry_in := a(index) and carry_in;
|
end loop;
|
end loop;
|
return result;
|
return result;
|
end; --function
|
end; --function
|
