OpenCores
URL https://opencores.org/ocsvn/plasma/plasma/trunk

Subversion Repositories plasma

[/] [plasma/] [trunk/] [vhdl/] [mlite_pack.vhd] - Diff between revs 285 and 332

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 285 Rev 332
Line 108... Line 108...
   function bv_inc(a : in std_logic_vector
   function bv_inc(a : in std_logic_vector
                  ) return std_logic_vector;
                  ) return std_logic_vector;
 
 
   -- For Altera
   -- For Altera
   COMPONENT lpm_ram_dp
   COMPONENT lpm_ram_dp
      GENERIC (
      generic (
         lpm_width        : NATURAL;
         LPM_WIDTH : natural;    -- MUST be greater than 0
         lpm_widthad      : NATURAL;
         LPM_WIDTHAD : natural;    -- MUST be greater than 0
         rden_used        : STRING;
         LPM_NUMWORDS : natural := 0;
         intended_device_family : STRING;
         LPM_INDATA : string := "REGISTERED";
         lpm_indata       : STRING;
         LPM_OUTDATA : string := "REGISTERED";
         lpm_wraddress_control          : STRING;
         LPM_RDADDRESS_CONTROL : string := "REGISTERED";
         lpm_rdaddress_control          : STRING;
         LPM_WRADDRESS_CONTROL : string := "REGISTERED";
         lpm_outdata      : STRING;
         LPM_FILE : string := "UNUSED";
         use_eab          : STRING;
         LPM_TYPE : string := "LPM_RAM_DP";
         lpm_type         : STRING);
         USE_EAB  : string := "OFF";
      PORT (
         INTENDED_DEVICE_FAMILY  : string := "UNUSED";
         wren      : IN STD_LOGIC ;
         RDEN_USED  : string := "TRUE";
         wrclock   : IN STD_LOGIC ;
         LPM_HINT : string := "UNUSED");
         q         : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
      port (
         data      : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
         RDCLOCK   : in std_logic := '0';
         rdaddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0);
         RDCLKEN   : in std_logic := '1';
         wraddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0));
         RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
 
         RDEN      : in std_logic := '1';
 
         DATA      : in std_logic_vector(LPM_WIDTH-1 downto 0);
 
         WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
 
         WREN      : in std_logic;
 
         WRCLOCK   : in std_logic := '0';
 
         WRCLKEN   : in std_logic := '1';
 
         Q         : out std_logic_vector(LPM_WIDTH-1 downto 0));
   END COMPONENT;
   END COMPONENT;
 
 
   -- For Altera
   -- For Altera
   component LPM_RAM_DQ
   component LPM_RAM_DQ
      generic (
      generic (

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.