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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Multiplication and Division Unit
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-- TITLE: Multiplication and Division Unit
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-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)
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-- Matthias Gruenewald
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-- DATE CREATED: 1/31/01
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-- DATE CREATED: 1/31/01
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-- FILENAME: mult.vhd
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-- FILENAME: mult.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Implements the multiplication and division unit.
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-- Implements the multiplication and division unit in 32 clocks.
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-- Division takes 32 clock cycles.
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-- Multiplication normally takes 16 clock cycles.
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-- if b <= 0xffff then mult in 8 cycles.
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-- if b <= 0xff then mult in 4 cycles.
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--
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--
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-- For multiplication set reg_b = 0x00000000 & b. The 64-bit result
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-- MULTIPLICATION
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-- will be in reg_b. The lower bits of reg_b contain the upper
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-- long64 answer = 0
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-- bits of b that have not yet been multiplied. For 16 clock cycles
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-- for(i = 0; i < 32; ++i)
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-- shift reg_b two bits to the right. Use the lowest two bits of reg_b
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-- {
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-- to multiply by two bits at a time and add the result to the upper
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-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
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-- 32-bits of reg_b (using C syntax):
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-- b = b >> 1;
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-- reg_b = (reg_b >> 2) + (((reg_b & 3) * reg_a) << 32);
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-- }
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--
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--
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-- For division set reg_b = '0' & b & 30_ZEROS. The answer will be
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-- DIVISION
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-- in answer_reg and the remainder in reg_a. For 32 clock cycles
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-- long upper=a, lower=0;
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-- (using C syntax):
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-- a = b << 31;
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-- answer_reg = (answer_reg << 1);
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-- for(i = 0; i < 32; ++i)
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-- if (reg_a >= reg_b) {
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-- {
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-- answer_reg += 1;
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-- lower = lower << 1;
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-- reg_a -= reg_b;
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-- if(upper >= a && a && b < 2)
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-- {
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-- upper = upper - a;
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-- lower |= 1;
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-- }
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-- a = ((b&2) << 30) | (a >> 1);
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-- b = b >> 1;
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-- }
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-- }
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-- reg_b = reg_b >> 1;
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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--library ieee, MLITE_LIB;
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--use MLITE_LIB.all;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity mult is
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entity mult is
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generic(adder_type : string := "DEFAULT";
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generic(mult_type : string := "DEFAULT");
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mult_type : string := "DEFAULT");
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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a, b : in std_logic_vector(31 downto 0);
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a, b : in std_logic_vector(31 downto 0);
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mult_func : in mult_function_type;
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mult_func : in mult_function_type;
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c_mult : out std_logic_vector(31 downto 0);
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c_mult : out std_logic_vector(31 downto 0);
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pause_out : out std_logic);
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pause_out : out std_logic);
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end; --entity mult
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end; --entity mult
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architecture logic of mult is
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architecture logic of mult is
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signal do_mult_reg : std_logic;
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constant MODE_MULT : std_logic := '1';
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signal do_signed_reg : std_logic;
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constant MODE_DIV : std_logic := '0';
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signal mode_reg : std_logic;
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signal negate_reg : std_logic;
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signal sign_reg : std_logic;
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signal sign2_reg : std_logic;
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signal count_reg : std_logic_vector(5 downto 0);
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signal count_reg : std_logic_vector(5 downto 0);
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signal reg_a : std_logic_vector(31 downto 0);
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signal aa_reg : std_logic_vector(31 downto 0);
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signal reg_b : std_logic_vector(63 downto 0);
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signal bb_reg : std_logic_vector(31 downto 0);
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signal answer_reg : std_logic_vector(31 downto 0);
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signal upper_reg : std_logic_vector(31 downto 0);
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signal aa, bb : std_logic_vector(33 downto 0);
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signal lower_reg : std_logic_vector(31 downto 0);
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signal sum : std_logic_vector(33 downto 0);
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signal reg_a_times3 : std_logic_vector(33 downto 0);
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signal a_neg : std_logic_vector(31 downto 0);
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signal sign_extend_sig : std_logic;
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signal b_neg : std_logic_vector(31 downto 0);
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signal a_neg_sig : std_logic_vector(31 downto 0);
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signal sum : std_logic_vector(32 downto 0);
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signal b_neg_sig : std_logic_vector(31 downto 0);
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--Used in Xilinx tri-state area optimizated version
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signal a_temp_sig : std_logic_vector(31 downto 0);
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signal b_temp_sig : std_logic_vector(63 downto 0);
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signal a_msb, b_msb : std_logic;
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signal answer_temp_sig : std_logic_vector(31 downto 0);
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signal aa_select : std_logic_vector(3 downto 0);
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signal bb_select : std_logic_vector(1 downto 0);
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signal a_select : std_logic_vector(4 downto 0);
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signal b_select : std_logic_vector(11 downto 0);
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signal answer_select : std_logic_vector(2 downto 0);
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begin
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begin
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--sum = aa + bb
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generic_adder: if adder_type = "DEFAULT" generate
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sum <= (aa + bb) when do_mult_reg = '1' else
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(aa - bb);
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end generate; --generic_adder
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--For Altera: sum = aa + bb
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lpm_adder: if adder_type = "ALTERA" generate
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lpm_add_sub_component : lpm_add_sub
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GENERIC MAP (
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lpm_width => 34,
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lpm_direction => "UNUSED",
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lpm_type => "LPM_ADD_SUB",
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lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
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)
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PORT MAP (
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dataa => aa,
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add_sub => do_mult_reg,
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datab => bb,
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result => sum
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);
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end generate; --lpm_adder
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-- Negate signals
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a_neg_sig <= bv_negate(a);
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b_neg_sig <= bv_negate(b);
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sign_extend_sig <= do_signed_reg and do_mult_reg;
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-- Result
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-- Result
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c_mult <= reg_b(31 downto 0) when mult_func = MULT_READ_LO else
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c_mult <= lower_reg when mult_func = MULT_READ_LO and negate_reg = '0' else
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reg_b(63 downto 32) when mult_func = MULT_READ_HI else
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bv_negate(lower_reg) when mult_func = MULT_READ_LO
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and negate_reg = '1' else
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upper_reg when mult_func = MULT_READ_HI else
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ZERO;
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ZERO;
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pause_out <= '1' when (count_reg /= "000000") and
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(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) else '0';
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-- ABS and remainder signals
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GENERIC_MULT: if MULT_TYPE = "DEFAULT" generate
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a_neg <= bv_negate(a);
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b_neg <= bv_negate(b);
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sum <= bv_adder(upper_reg, aa_reg, mode_reg);
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--multiplication/division unit
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--multiplication/division unit
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mult_proc: process(clk, reset_in, a, b, mult_func,
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mult_proc: process(clk, reset_in, a, b, mult_func,
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do_mult_reg, do_signed_reg, count_reg,
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a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
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reg_a, reg_b, answer_reg, sum, reg_a_times3)
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count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
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variable do_mult_temp : std_logic;
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variable count : std_logic_vector(2 downto 0);
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variable do_signed_temp : std_logic;
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variable count_temp : std_logic_vector(5 downto 0);
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variable a_temp : std_logic_vector(31 downto 0);
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variable b_temp : std_logic_vector(63 downto 0);
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variable answer_temp : std_logic_vector(31 downto 0);
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variable start : std_logic;
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variable do_write : std_logic;
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variable do_hi : std_logic;
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variable sign_extend : std_logic;
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begin
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begin
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do_mult_temp := do_mult_reg;
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count := "001";
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do_signed_temp := do_signed_reg;
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count_temp := count_reg;
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a_temp := reg_a;
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b_temp := reg_b;
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answer_temp := answer_reg;
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sign_extend := do_signed_reg and do_mult_reg;
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start := '0';
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do_write := '0';
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do_hi := '0';
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case mult_func is
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when MULT_READ_LO =>
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when MULT_READ_HI =>
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do_hi := '1';
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when MULT_WRITE_LO =>
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do_write := '1';
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when MULT_WRITE_HI =>
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do_write := '1';
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do_hi := '1';
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when MULT_MULT =>
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start := '1';
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do_mult_temp := '1';
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do_signed_temp := '0';
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when MULT_SIGNED_MULT =>
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start := '1';
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do_mult_temp := '1';
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do_signed_temp := '1';
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when MULT_DIVIDE =>
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start := '1';
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do_mult_temp := '0';
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do_signed_temp := '0';
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when MULT_SIGNED_DIVIDE =>
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start := '1';
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do_mult_temp := '0';
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do_signed_temp := a(31) xor b(31);
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when others =>
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end case;
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if start = '1' then
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count_temp := "000000";
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answer_temp := ZERO;
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if do_mult_temp = '0' then
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b_temp(63) := '0';
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if mult_func /= MULT_SIGNED_DIVIDE or a(31) = '0' then
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a_temp := a;
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else
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a_temp := a_neg_sig;
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end if;
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if mult_func /= MULT_SIGNED_DIVIDE or b(31) = '0' then
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b_temp(62 downto 31) := b;
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else
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b_temp(62 downto 31) := b_neg_sig;
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end if;
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b_temp(30 downto 0) := ZERO(30 downto 0);
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else --multiply
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if do_signed_temp = '0' or b(31) = '0' then
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a_temp := a;
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b_temp(31 downto 0) := b;
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else
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a_temp := a_neg_sig;
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b_temp(31 downto 0) := b_neg_sig;
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end if;
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b_temp(63 downto 32) := ZERO;
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end if;
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elsif do_write = '1' then
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if do_hi = '0' then
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b_temp(31 downto 0) := a;
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else
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b_temp(63 downto 32) := a;
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end if;
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end if;
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if do_mult_reg = '0' then --division
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aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;
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bb <= reg_b(33 downto 0);
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else --multiplication two-bits at a time
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case reg_b(1 downto 0) is
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when "00" =>
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aa <= "00" & ZERO;
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when "01" =>
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aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;
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when "10" =>
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aa <= (reg_a(31) and sign_extend) & reg_a & '0';
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when others =>
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aa <= reg_a_times3;
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end case;
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bb <= (reg_b(63) and sign_extend) & (reg_b(63) and sign_extend) & reg_b(63 downto 32);
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end if;
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if count_reg(5) = '0' and start = '0' then
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count_temp := bv_inc6(count_reg);
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if do_mult_reg = '0' then --division
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answer_temp(31 downto 1) := answer_reg(30 downto 0);
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if reg_b(63 downto 32) = ZERO and sum(32) = '0' then
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a_temp := sum(31 downto 0); --aa=aa-bb;
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answer_temp(0) := '1';
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else
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answer_temp(0) := '0';
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end if;
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if count_reg /= "011111" then
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b_temp(62 downto 0) := reg_b(63 downto 1);
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else --done with divide
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b_temp(63 downto 32) := a_temp;
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if do_signed_reg = '0' then
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b_temp(31 downto 0) := answer_temp;
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else
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b_temp(31 downto 0) := bv_negate(answer_temp);
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end if;
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end if;
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else -- mult_mode
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b_temp(63 downto 30) := sum;
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b_temp(29 downto 0) := reg_b(31 downto 2);
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if count_reg = "001000" and sign_extend = '0' and --early stop
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reg_b(15 downto 0) = ZERO(15 downto 0) then
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count_temp := "111111";
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b_temp(31 downto 0) := reg_b(47 downto 16);
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end if;
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if count_reg = "000100" and sign_extend = '0' and --early stop
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reg_b(23 downto 0) = ZERO(23 downto 0) then
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count_temp := "111111";
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b_temp(31 downto 0) := reg_b(55 downto 24);
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end if;
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count_temp(5) := count_temp(4);
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end if;
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end if;
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if reset_in = '1' then
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if reset_in = '1' then
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do_mult_reg <= '0';
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mode_reg <= '0';
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do_signed_reg <= '0';
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negate_reg <= '0';
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sign_reg <= '0';
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sign2_reg <= '0';
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count_reg <= "000000";
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count_reg <= "000000";
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reg_a <= ZERO;
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aa_reg <= ZERO;
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reg_b <= ZERO & ZERO;
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bb_reg <= ZERO;
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answer_reg <= ZERO;
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upper_reg <= ZERO;
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reg_a_times3 <= "00" & ZERO;
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lower_reg <= ZERO;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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do_mult_reg <= do_mult_temp;
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do_signed_reg <= do_signed_temp;
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count_reg <= count_temp;
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reg_a <= a_temp;
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reg_b <= b_temp;
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answer_reg <= answer_temp;
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if start = '1' then
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reg_a_times3 <= ((a_temp(31) and do_signed_temp) & a_temp & '0') +
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((a_temp(31) and do_signed_temp) & (a_temp(31) and do_signed_temp) & a_temp);
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end if;
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end if;
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if count_reg(5) = '0' and mult_func /= mult_nothing and start = '0' then
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pause_out <= '1';
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else
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pause_out <= '0';
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end if;
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end process;
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--Only used in Xilinx tri-state area optimizated version
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a_temp_sig <= ZERO;
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b_temp_sig <= ZERO & ZERO;
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a_msb <= '0';
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b_msb <= '0';
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answer_temp_sig <= ZERO;
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aa_select <= "0000";
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bb_select <= "00";
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a_select <= "00000";
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b_select <= ZERO(11 downto 0);
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answer_select <= "000";
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end generate;
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AREA_OPTIMIZED_MULT: if MULT_TYPE="AREA_OPTIMIZED" generate
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--Xilinx Tristate size optimization by Matthias Gruenewald
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--multiplication/division unit
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mult_proc: process(a, b, clk, count_reg, do_mult_reg, do_signed_reg, mult_func, reg_b, sum)
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variable do_mult_temp : std_logic;
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variable do_signed_temp : std_logic;
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variable count_temp : std_logic_vector(5 downto 0);
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variable start : std_logic;
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variable do_write : std_logic;
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variable do_hi : std_logic;
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variable sign_extend : std_logic;
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begin
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do_mult_temp := do_mult_reg;
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do_signed_temp := do_signed_reg;
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count_temp := count_reg;
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sign_extend := do_signed_reg and do_mult_reg;
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sign_extend_sig <= sign_extend;
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start := '0';
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do_write := '0';
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do_hi := '0';
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a_select <= (others => '0');
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b_select <= (others => '0');
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aa_select <= (others => '0');
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bb_select <= (others => '0');
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answer_select <= (others => '0');
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case mult_func is
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case mult_func is
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when MULT_READ_LO =>
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when MULT_READ_HI =>
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do_hi := '1';
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when MULT_WRITE_LO =>
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when MULT_WRITE_LO =>
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do_write := '1';
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lower_reg <= a;
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negate_reg <= '0';
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when MULT_WRITE_HI =>
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when MULT_WRITE_HI =>
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do_write := '1';
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upper_reg <= a;
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do_hi := '1';
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negate_reg <= '0';
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when MULT_MULT =>
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when MULT_MULT =>
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start := '1';
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mode_reg <= MODE_MULT;
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do_mult_temp := '1';
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aa_reg <= a;
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do_signed_temp := '0';
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bb_reg <= b;
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upper_reg <= ZERO;
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count_reg <= "100000";
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negate_reg <= '0';
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sign_reg <= '0';
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sign2_reg <= '0';
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when MULT_SIGNED_MULT =>
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when MULT_SIGNED_MULT =>
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start := '1';
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mode_reg <= MODE_MULT;
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do_mult_temp := '1';
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if b(31) = '0' then
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do_signed_temp := '1';
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aa_reg <= a;
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bb_reg <= b;
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sign_reg <= a(31);
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else
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aa_reg <= a_neg;
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bb_reg <= b_neg;
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sign_reg <= a_neg(31);
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end if;
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sign2_reg <= '0';
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upper_reg <= ZERO;
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count_reg <= "100000";
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negate_reg <= '0';
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when MULT_DIVIDE =>
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when MULT_DIVIDE =>
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start := '1';
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mode_reg <= MODE_DIV;
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do_mult_temp := '0';
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aa_reg <= b(0) & ZERO(30 downto 0);
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do_signed_temp := '0';
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bb_reg <= b;
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upper_reg <= a;
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count_reg <= "100000";
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negate_reg <= '0';
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when MULT_SIGNED_DIVIDE =>
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when MULT_SIGNED_DIVIDE =>
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start := '1';
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mode_reg <= MODE_DIV;
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do_mult_temp := '0';
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if b(31) = '0' then
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do_signed_temp := a(31) xor b(31);
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aa_reg(31) <= b(0);
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bb_reg <= b;
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else
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aa_reg(31) <= b_neg(0);
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bb_reg <= b_neg;
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end if;
|
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if a(31) = '0' then
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upper_reg <= a;
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else
|
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upper_reg <= a_neg;
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|
end if;
|
|
aa_reg(30 downto 0) <= ZERO(30 downto 0);
|
|
count_reg <= "100000";
|
|
negate_reg <= a(31) xor b(31);
|
when others =>
|
when others =>
|
end case;
|
|
|
|
if start = '1' then
|
if count_reg /= "000000" then
|
count_temp := "000000";
|
if mode_reg = MODE_MULT then
|
answer_select(0)<='1';
|
-- Multiplication
|
--answer_temp := ZERO;
|
if bb_reg(0) = '1' then
|
if do_mult_temp = '0' then
|
upper_reg <= (sign_reg xor sum(32)) & sum(31 downto 1);
|
--b_temp(63) := '0';
|
lower_reg <= sum(0) & lower_reg(31 downto 1);
|
if mult_func /= MULT_SIGNED_DIVIDE or a(31) = '0' then
|
sign2_reg <= sign2_reg or sign_reg;
|
a_select(0) <= '1';
|
sign_reg <= '0';
|
--a_temp := a;
|
bb_reg <= '0' & bb_reg(31 downto 1);
|
else
|
-- The following six lines are optional for speedup
|
a_select(1) <= '1';
|
elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
|
--a_temp := a_neg;
|
count_reg(5 downto 2) /= "0000" then
|
end if;
|
upper_reg <= "0000" & upper_reg(31 downto 4);
|
if mult_func /= MULT_SIGNED_DIVIDE or b(31) = '0' then
|
lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
|
b_select(0) <= '1';
|
count := "100";
|
--b_temp(62 downto 31) := b;
|
bb_reg <= "0000" & bb_reg(31 downto 4);
|
else
|
else
|
b_select(1) <= '1';
|
upper_reg <= sign2_reg & upper_reg(31 downto 1);
|
--b_temp(62 downto 31) := b_neg;
|
lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
|
end if;
|
bb_reg <= '0' & bb_reg(31 downto 1);
|
--b_temp(30 downto 0) := ZERO(30 downto 0);
|
end if;
|
else --multiply
|
else
|
if do_signed_temp = '0' or b(31) = '0' then
|
-- Division
|
a_select(2) <= '1';
|
if sum(32) = '0' and aa_reg /= ZERO and
|
--a_temp := a;
|
bb_reg(31 downto 1) = ZERO(31 downto 1) then
|
b_select(2) <= '1';
|
upper_reg <= sum(31 downto 0);
|
--b_temp(31 downto 0) := b;
|
lower_reg(0) <= '1';
|
else
|
else
|
a_select(3) <= '1';
|
lower_reg(0) <= '0';
|
--a_temp := a_neg;
|
end if;
|
b_select(3) <= '1';
|
aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
|
--b_temp(31 downto 0) := b_neg;
|
lower_reg(31 downto 1) <= lower_reg(30 downto 0);
|
end if;
|
bb_reg <= '0' & bb_reg(31 downto 1);
|
--b_temp(63 downto 32) := ZERO;
|
|
end if;
|
|
elsif do_write = '1' then
|
|
if do_hi = '0' then
|
|
b_select(4) <= '1';
|
|
--b_temp(31 downto 0) := a;
|
|
else
|
|
b_select(5) <= '1';
|
|
--b_temp(63 downto 32) := a;
|
|
end if;
|
|
end if;
|
end if;
|
|
count_reg <= count_reg - count;
|
|
end if; --count
|
|
|
if do_mult_reg = '0' then --division
|
|
aa_select(0) <= '1';
|
|
--aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;
|
|
bb_select(0) <= '1';
|
|
--bb <= reg_b(33 downto 0);
|
|
else --multiplication two-bits at a time
|
|
case reg_b(1 downto 0) is
|
|
when "00" =>
|
|
aa_select(1) <= '1';
|
|
--aa <= "00" & ZERO;
|
|
when "01" =>
|
|
aa_select(2) <= '1';
|
|
--aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;
|
|
when "10" =>
|
|
aa_select(3) <= '1';
|
|
--aa <= (reg_a(31) and sign_extend) & reg_a & '0';
|
|
when others =>
|
|
--aa_select(4) <= '1';
|
|
--aa <= reg_a_times3;
|
|
end case;
|
end case;
|
bb_select(1) <= '1';
|
|
--bb <= (reg_b(63) and sign_extend) & (reg_b(63) and sign_extend) & reg_b(63 downto 32);
|
|
end if;
|
|
|
|
if count_reg(5) = '0' and start = '0' then
|
|
count_temp := bv_inc6(count_reg);
|
|
if do_mult_reg = '0' then --division
|
|
--answer_temp(31 downto 1) := answer_reg(30 downto 0);
|
|
if reg_b(63 downto 32) = ZERO and sum(32) = '0' then
|
|
a_select(4) <= '1';
|
|
--a_temp := sum(31 downto 0); --aa=aa-bb;
|
|
answer_select(1) <= '1';
|
|
--answer_temp(0) := '1';
|
|
else
|
|
answer_select(2) <= '1';
|
|
--answer_temp(0) := '0';
|
|
end if;
|
|
if count_reg /= "011111" then
|
|
--b_temp(62 downto 0) := reg_b(63 downto 1);
|
|
b_select(6) <= '1';
|
|
else --done with divide
|
|
--b_temp(63 downto 32) := a_temp;
|
|
if do_signed_reg = '0' then
|
|
b_select(7) <= '1';
|
|
--b_temp(31 downto 0) := answer_temp;
|
|
else
|
|
b_select(8) <= '1';
|
|
--b_temp(31 downto 0) := bv_negate(answer_temp);
|
|
end if;
|
|
end if;
|
|
else -- mult_mode
|
|
b_select(9) <= '1';
|
|
--b_temp(63 downto 30) := sum;
|
|
--b_temp(29 downto 0) := reg_b(31 downto 2);
|
|
if count_reg = "001000" and sign_extend = '0' and --early stop
|
|
reg_b(15 downto 0) = ZERO(15 downto 0) then
|
|
count_temp := "111111";
|
|
b_select(10) <= '1';
|
|
--b_temp(31 downto 0) := reg_b(47 downto 16);
|
|
end if;
|
|
if count_reg = "000100" and sign_extend = '0' and --early stop
|
|
reg_b(23 downto 0) = ZERO(23 downto 0) then
|
|
count_temp := "111111";
|
|
b_select(11) <= '1';
|
|
--b_temp(31 downto 0) := reg_b(55 downto 24);
|
|
end if;
|
|
count_temp(5) := count_temp(4);
|
|
end if;
|
|
end if;
|
|
|
|
if reset_in = '1' then
|
|
do_mult_reg <= '0';
|
|
do_signed_reg <= '0';
|
|
count_reg <= "000000";
|
|
reg_a <= ZERO;
|
|
reg_b <= ZERO & ZERO;
|
|
answer_reg <= ZERO;
|
|
reg_a_times3 <= "00" & ZERO;
|
|
elsif rising_edge(clk) then
|
|
do_mult_reg <= do_mult_temp;
|
|
do_signed_reg <= do_signed_temp;
|
|
count_reg <= count_temp;
|
|
reg_a <= a_temp_sig;
|
|
reg_b <= b_temp_sig;
|
|
answer_reg <= answer_temp_sig;
|
|
if start = '1' then
|
|
reg_a_times3 <= ((a_temp_sig(31) and do_signed_temp) & a_temp_sig & '0') +
|
|
((a_temp_sig(31) and do_signed_temp) & (a_temp_sig(31) and do_signed_temp) & a_temp_sig);
|
|
end if;
|
|
end if;
|
|
|
|
if count_reg(5) = '0' and mult_func/= mult_nothing and start = '0' then
|
|
pause_out <= '1';
|
|
else
|
|
pause_out <= '0';
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
|
|
|
|
-- Arguments
|
|
a_msb <= reg_a(31) and sign_extend_sig;
|
|
aa <= a_msb & a_msb & reg_a when aa_select(0)='1' else
|
|
"00" & ZERO when aa_select(1)='1' else
|
|
a_msb & a_msb & reg_a when aa_select(2)='1' else
|
|
a_msb & reg_a & '0' when aa_select(3)='1' else
|
|
reg_a_times3;
|
|
|
|
b_msb <= reg_b(63) and sign_extend_sig;
|
|
bb <= reg_b(33 downto 0) when bb_select(0)='1' else (others => 'Z');
|
|
bb <= b_msb & b_msb & reg_b(63 downto 32) when bb_select(1)='1' else (others => 'Z');
|
|
|
|
-- Divide: Init
|
|
a_temp_sig <= a when a_select(0)='1' else (others => 'Z');
|
|
a_temp_sig <= a_neg_sig when a_select(1)='1' else (others => 'Z');
|
|
b_temp_sig <= '0' & b & ZERO(30 downto 0) when b_select(0)='1' else (others => 'Z');
|
|
b_temp_sig <= '0' & b_neg_sig & ZERO(30 downto 0) when b_select(1)='1' else (others => 'Z');
|
|
|
|
-- Multiply: Init
|
|
a_temp_sig <= a when a_select(2)='1' else (others => 'Z');
|
|
b_temp_sig <= ZERO & b when b_select(2)='1' else (others => 'Z');
|
|
a_temp_sig <= a_neg_sig when a_select(3)='1' else (others => 'Z');
|
|
b_temp_sig <= ZERO & b_neg_sig when b_select(3)='1' else (others => 'Z');
|
|
|
|
-- Intermediate results
|
|
b_temp_sig <= reg_b(63 downto 32) & a when b_select(4)='1' else (others => 'Z');
|
|
b_temp_sig <= a & reg_b(31 downto 0) when b_select(5)='1' else (others => 'Z');
|
|
|
|
-- Divide: Operation
|
|
a_temp_sig <= sum(31 downto 0) when a_select(4)='1' else (others => 'Z');
|
|
b_temp_sig <= reg_b(63) & reg_b(63 downto 1) when b_select(6)='1' else (others => 'Z');
|
|
b_temp_sig <= a_temp_sig & answer_temp_sig when b_select(7)='1' else (others => 'Z');
|
|
b_temp_sig <= a_temp_sig & bv_negate(answer_temp_sig) when b_select(8)='1' else (others => 'Z');
|
|
|
|
-- Multiply: Operation
|
|
b_temp_sig <= sum & reg_b(31 downto 2) when b_select(9)='1' and b_select(10)='0' and b_select(11)='0' else (others => 'Z');
|
|
b_temp_sig <= sum(33 downto 2) & reg_b(47 downto 16) when b_select(10)='1' else (others => 'Z');
|
|
b_temp_sig <= sum(33 downto 2) & reg_b(55 downto 24) when b_select(11)='1' else (others => 'Z');
|
|
|
|
-- Default values
|
|
a_temp_sig <= reg_a when conv_integer(unsigned(a_select))=0 else (others => 'Z');
|
|
b_temp_sig <= reg_b when conv_integer(unsigned(b_select))=0 else (others => 'Z');
|
|
|
|
-- Result
|
|
answer_temp_sig <= ZERO when answer_select(0)='1' else
|
|
answer_reg(30 downto 0) & '1' when answer_select(1)='1' else
|
|
answer_reg(30 downto 0) & '0' when answer_select(2)='1' else
|
|
answer_reg;
|
|
|
|
end generate;
|
|
|
|
end; --architecture logic
|
end; --architecture logic
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
