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Line 50... |
variable aa, bb : std_logic_vector(32 downto 0);
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variable aa, bb : std_logic_vector(32 downto 0);
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variable sum : std_logic_vector(32 downto 0);
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variable sum : std_logic_vector(32 downto 0);
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variable start : std_logic;
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variable start : std_logic;
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variable do_write : std_logic;
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variable do_write : std_logic;
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variable do_hi : std_logic;
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variable do_hi : std_logic;
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variable sign_extend : std_logic;
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begin
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begin
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do_div_temp := do_div_reg;
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do_div_temp := do_div_reg;
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do_signed_temp := do_signed_reg;
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do_signed_temp := do_signed_reg;
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count_temp := count_reg;
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count_temp := count_reg;
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a_temp := reg_a;
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a_temp := reg_a;
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b_temp := reg_b;
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b_temp := reg_b;
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answer_temp := answer_reg;
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answer_temp := answer_reg;
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sign_extend := do_signed_reg and not do_div_reg;
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aa := '0' & ZERO;
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aa := '0' & ZERO;
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bb := '0' & ZERO;
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bb := '0' & ZERO;
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sum := '0' & ZERO;
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sum := '0' & ZERO;
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start := '0';
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start := '0';
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Line 80... |
do_write := '1';
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do_write := '1';
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do_hi := '1';
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do_hi := '1';
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when mult_mult =>
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when mult_mult =>
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start := '1';
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start := '1';
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do_div_temp := '0';
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do_div_temp := '0';
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do_signed_temp := '0';
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when mult_signed_mult =>
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start := '1';
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do_div_temp := '0';
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do_signed_temp := a(31) xor b(31);
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when mult_divide =>
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when mult_divide =>
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start := '1';
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start := '1';
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do_div_temp := '1';
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do_div_temp := '1';
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do_signed_temp := '0';
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do_signed_temp := '0';
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when mult_signed_divide =>
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when mult_signed_divide =>
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end if;
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end if;
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if do_div_reg = '1' then
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if do_div_reg = '1' then
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bb := reg_b(32 downto 0);
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bb := reg_b(32 downto 0);
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else
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else
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bb := '0' & reg_b(63 downto 32);
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-- bb := '0' & reg_b(63 downto 32);
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bb := (reg_b(63) and sign_extend) & reg_b(63 downto 32);
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end if;
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end if;
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aa := '0' & reg_a;
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-- aa := '0' & reg_a;
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aa := (reg_a(31) and sign_extend) & reg_a;
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sum := bv_adder(aa, bb, do_div_reg);
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sum := bv_adder(aa, bb, do_div_reg);
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-- sum := bv_adder_lookahead(aa, bb, do_div_reg);
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-- sum := bv_adder_lookahead(aa, bb, do_div_reg);
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if count_reg(5) = '0' and start = '0' then
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if count_reg(5) = '0' and start = '0' then
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count_temp := bv_inc6(count_reg);
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count_temp := bv_inc6(count_reg);
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Line 159... |
end if;
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end if;
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else -- mult_mode
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else -- mult_mode
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if reg_b(0) = '1' then
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if reg_b(0) = '1' then
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b_temp(63 downto 31) := sum;
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b_temp(63 downto 31) := sum;
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else
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else
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b_temp(63 downto 31) := '0' & reg_b(63 downto 32);
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b_temp(63 downto 31) := sign_extend & reg_b(63 downto 32);
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if reg_b(63 downto 32) = ZERO then
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b_temp(63) := '0';
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end if;
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end if;
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end if;
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b_temp(30 downto 0) := reg_b(31 downto 1);
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b_temp(30 downto 0) := reg_b(31 downto 1);
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if count_reg = "010000" and --early stop
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if count_reg = "010000" and sign_extend = '0' and --early stop
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reg_b(15 downto 0) = ZERO(15 downto 0) then
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reg_b(15 downto 0) = ZERO(15 downto 0) then
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count_temp := "111111";
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count_temp := "111111";
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b_temp(31 downto 0) := reg_b(47 downto 16);
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b_temp(31 downto 0) := reg_b(47 downto 16);
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end if;
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end if;
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if count_reg = "001000" and --early stop
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if count_reg = "001000" and sign_extend = '0' and --early stop
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reg_b(23 downto 0) = ZERO(23 downto 0) then
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reg_b(23 downto 0) = ZERO(23 downto 0) then
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count_temp := "111111";
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count_temp := "111111";
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b_temp(31 downto 0) := reg_b(55 downto 24);
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b_temp(31 downto 0) := reg_b(55 downto 24);
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end if;
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end if;
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end if;
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end if;
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Line 205... |
end process;
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end process;
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end; --architecture logic
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end; --architecture logic
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