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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Implements the multiplication and division unit.
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-- Implements the multiplication and division unit.
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-- Normally takes 32 clock cycles.
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-- Normally takes 32 clock cycles.
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-- if b(31 downto 16) = ZERO(31 downto 16) then mult in 16 cycles.
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-- if b(31 downto 8) = ZERO(31 downto 8) then mult in 8 cycles.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mips_pack.all;
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use work.mips_pack.all;
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b_temp(62 downto 31) := bv_negate(b);
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b_temp(62 downto 31) := bv_negate(b);
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a_temp := bv_negate(a);
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a_temp := bv_negate(a);
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end if;
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end if;
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b_temp(30 downto 0) := ZERO(30 downto 0);
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b_temp(30 downto 0) := ZERO(30 downto 0);
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else --multiply
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else --multiply
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b_temp := zero & b;
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b_temp := ZERO & b;
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end if;
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end if;
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elsif do_write = '1' then
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elsif do_write = '1' then
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if do_hi = '0' then
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if do_hi = '0' then
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b_temp(31 downto 0) := a;
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b_temp(31 downto 0) := a;
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else
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else
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Line 148... |
else
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else
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b_temp(63 downto 31) := '0' & reg_b(63 downto 32);
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b_temp(63 downto 31) := '0' & reg_b(63 downto 32);
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end if;
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end if;
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b_temp(30 downto 0) := reg_b(31 downto 1);
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b_temp(30 downto 0) := reg_b(31 downto 1);
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if count_reg = "010000" and --early stop
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if count_reg = "010000" and --early stop
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reg_b(15 downto 0) = zero(15 downto 0) then
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reg_b(15 downto 0) = ZERO(15 downto 0) then
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count_temp := "111111";
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count_temp := "111111";
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b_temp(31 downto 0) := reg_b(47 downto 16);
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b_temp(31 downto 0) := reg_b(47 downto 16);
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end if;
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end if;
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if count_reg = "001000" and --early stop
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reg_b(23 downto 0) = ZERO(23 downto 0) then
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count_temp := "111111";
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b_temp(31 downto 0) := reg_b(55 downto 24);
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end if;
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end if;
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end if;
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end if;
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end if;
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if rising_edge(clk) then
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if rising_edge(clk) then
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do_div_reg <= do_div_temp;
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do_div_reg <= do_div_temp;
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Line 179... |
if mult_func = mult_read_lo then
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if mult_func = mult_read_lo then
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c_mult <= reg_b(31 downto 0);
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c_mult <= reg_b(31 downto 0);
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elsif mult_func = mult_read_hi then
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elsif mult_func = mult_read_hi then
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c_mult <= reg_b(63 downto 32);
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c_mult <= reg_b(63 downto 32);
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else
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else
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-- c_mult <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
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c_mult <= ZERO;
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c_mult <= ZERO;
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end if;
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end if;
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end process;
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end process;
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