| Line 59... |
Line 59... |
rd_index, rd_index_reg, pause_any, pause_reg,
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rd_index, rd_index_reg, pause_any, pause_reg,
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rs_index, rt_index,
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rs_index, rt_index,
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pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
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pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
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reg_dest, reg_dest_reg, c_bus)
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reg_dest, reg_dest_reg, c_bus)
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variable pause_mult_clock : std_logic;
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variable pause_mult_clock : std_logic;
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variable freeze_pipeline : std_logic;
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begin
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begin
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if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or
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if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or
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mem_source /= mem_fetch or
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mem_source /= mem_fetch or
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(mult_func = mult_read_lo or mult_func = mult_read_hi) then
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(mult_func = mult_read_lo or mult_func = mult_read_hi) then
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pause_mult_clock := '1';
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pause_mult_clock := '1';
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else
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else
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pause_mult_clock := '0';
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pause_mult_clock := '0';
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end if;
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end if;
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freeze_pipeline := not (pause_mult_clock and pause_reg) and pause_any;
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pause_pipeline <= pause_mult_clock and pause_reg;
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pause_pipeline <= pause_mult_clock and pause_reg;
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rd_indexD <= rd_index_reg;
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rd_indexD <= rd_index_reg;
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|
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if c_source_reg = c_from_alu then
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if c_source_reg = c_from_alu then
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reg_destD <= c_bus;
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reg_destD <= c_bus;
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else
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else
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reg_destD <= reg_dest_reg;
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reg_destD <= reg_dest_reg;
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end if;
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end if;
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if rising_edge(clk) then
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if rising_edge(clk) and freeze_pipeline = '0' then
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if (rs_index = "000000" or rs_index /= rd_index_reg) or
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if (rs_index = "000000" or rs_index /= rd_index_reg) or
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(a_source /= a_from_reg_source or pause_reg = '0') then
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(a_source /= a_from_reg_source or pause_reg = '0') then
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a_busD <= a_bus;
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a_busD <= a_bus;
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elsif c_source_reg = c_from_alu then
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elsif c_source_reg = c_from_alu then
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a_busD <= c_bus; --rs from previous operation (bypass stage)
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a_busD <= c_bus; --rs from previous operation (bypass stage)
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| Line 112... |
Line 114... |
if pause_reg = '0' and pause_any = '0' then
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if pause_reg = '0' and pause_any = '0' then
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pause_reg <= '1'; --enable pause_pipeline
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pause_reg <= '1'; --enable pause_pipeline
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elsif pause_mult_clock = '1' then
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elsif pause_mult_clock = '1' then
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pause_reg <= '0'; --disable pause_pipeline
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pause_reg <= '0'; --disable pause_pipeline
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end if;
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end if;
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if freeze_pipeline = '0' then
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rd_index_reg <= rd_index;
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rd_index_reg <= rd_index;
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end if;
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end if;
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end if;
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end process; --pipeline3
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end process; --pipeline3
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end; --logic
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end; --logic
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