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signal ram_byte_we : std_logic_vector(3 downto 0);
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signal ram_byte_we : std_logic_vector(3 downto 0);
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signal ram_address : std_logic_vector(31 downto 2);
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signal ram_address : std_logic_vector(31 downto 2);
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signal ram_data_w : std_logic_vector(31 downto 0);
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signal ram_data_w : std_logic_vector(31 downto 0);
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signal ram_data_r : std_logic_vector(31 downto 0);
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signal ram_data_r : std_logic_vector(31 downto 0);
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signal cache_check : std_logic;
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signal cache_access : std_logic;
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signal cache_checking : std_logic;
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signal cache_checking : std_logic;
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signal cache_miss : std_logic;
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signal cache_miss : std_logic;
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signal cache_hit : std_logic;
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signal cache_hit : std_logic;
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begin --architecture
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begin --architecture
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write_enable <= '1' when cpu_byte_we /= "0000" else '0';
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write_enable <= '1' when cpu_byte_we /= "0000" else '0';
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mem_busy <= eth_pause or mem_pause_in;
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mem_busy <= eth_pause or mem_pause_in;
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cache_hit <= cache_checking and not cache_miss;
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cache_hit <= cache_checking and not cache_miss;
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cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
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cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
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cache_miss or --Cache wait
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cache_miss or --Cache wait
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(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash --DDR in use
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(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
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irq_status <= gpioA_in(31) & not gpioA_in(31) &
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irq_status <= gpioA_in(31) & not gpioA_in(31) &
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irq_eth_send & irq_eth_rec &
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irq_eth_send & irq_eth_rec &
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counter_reg(18) & not counter_reg(18) &
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counter_reg(18) & not counter_reg(18) &
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not uart_write_busy & uart_data_avail;
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not uart_write_busy & uart_data_avail;
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irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
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irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
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data_w => cpu_data_w,
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data_w => cpu_data_w,
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data_r => cpu_data_r,
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data_r => cpu_data_r,
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mem_pause => cpu_pause);
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mem_pause => cpu_pause);
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opt_cache: if use_cache = '0' generate
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opt_cache: if use_cache = '0' generate
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cache_check <= '0';
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cache_access <= '0';
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cache_checking <= '0';
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cache_checking <= '0';
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cache_miss <= '0';
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cache_miss <= '0';
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end generate;
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end generate;
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opt_cache2: if use_cache = '1' generate
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opt_cache2: if use_cache = '1' generate
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address_next => address_next,
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address_next => address_next,
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byte_we_next => byte_we_next,
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byte_we_next => byte_we_next,
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cpu_address => cpu_address(31 downto 2),
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cpu_address => cpu_address(31 downto 2),
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mem_busy => mem_busy,
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mem_busy => mem_busy,
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cache_check => cache_check, --Stage1: address_next in first 2MB DDR
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cache_access => cache_access, --access 4KB cache
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cache_checking => cache_checking, --Stage2
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cache_checking => cache_checking, --checking if cache hit
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cache_miss => cache_miss); --Stage3
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cache_miss => cache_miss); --cache miss
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end generate; --opt_cache2
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end generate; --opt_cache2
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no_ddr_start <= not eth_pause and cache_checking;
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no_ddr_start <= not eth_pause and cache_checking;
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no_ddr_stop <= not eth_pause and cache_miss;
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no_ddr_stop <= not eth_pause and cache_miss;
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eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
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eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
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end if;
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end if;
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counter_reg <= bv_inc(counter_reg);
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counter_reg <= bv_inc(counter_reg);
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end if;
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end if;
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end process;
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end process;
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ram_enable <= '1' when address_next(30 downto 28) = "000" or
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ram_proc: process(cache_access, cache_miss,
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cache_check = '1' or cache_miss = '1' else '0';
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address_next, cpu_address,
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ram_byte_we <= byte_we_next when cache_miss = '0' else "1111";
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byte_we_next, cpu_data_w, data_read)
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ram_address(31 downto 13) <= ZERO(31 downto 13);
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begin
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ram_address(12 downto 2) <= (address_next(12) or cache_check) & address_next(11 downto 2)
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if cache_access = '1' then --Check if cache hit or write through
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when cache_miss = '0' else
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ram_enable <= '1';
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'1' & cpu_address(11 downto 2); --Update cache after cache miss
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ram_byte_we <= byte_we_next;
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ram_data_w <= cpu_data_w when cache_miss = '0' else data_read;
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ram_address(31 downto 2) <= ZERO(31 downto 16) &
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"0001" & address_next(11 downto 2);
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ram_data_w <= cpu_data_w;
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elsif cache_miss = '1' then --Update cache after cache miss
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ram_enable <= '1';
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ram_byte_we <= "1111";
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ram_address(31 downto 2) <= ZERO(31 downto 16) &
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"0001" & cpu_address(11 downto 2);
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ram_data_w <= data_read;
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else --Normal non-cache access
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if address_next(30 downto 28) = "000" then
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ram_enable <= '1';
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else
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ram_enable <= '0';
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end if;
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ram_byte_we <= byte_we_next;
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ram_address(31 downto 2) <= address_next(31 downto 2);
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ram_data_w <= cpu_data_w;
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end if;
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end process;
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u2_ram: ram
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u2_ram: ram
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generic map (memory_type => memory_type)
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generic map (memory_type => memory_type)
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port map (
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port map (
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clk => clk,
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clk => clk,
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