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[/] [plasma/] [trunk/] [vhdl/] [plasma.vhd] - Diff between revs 356 and 383

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Rev 356 Rev 383
Line 94... Line 94...
   signal ram_byte_we       : std_logic_vector(3 downto 0);
   signal ram_byte_we       : std_logic_vector(3 downto 0);
   signal ram_address       : std_logic_vector(31 downto 2);
   signal ram_address       : std_logic_vector(31 downto 2);
   signal ram_data_w        : std_logic_vector(31 downto 0);
   signal ram_data_w        : std_logic_vector(31 downto 0);
   signal ram_data_r        : std_logic_vector(31 downto 0);
   signal ram_data_r        : std_logic_vector(31 downto 0);
 
 
   signal cache_check       : std_logic;
   signal cache_access      : std_logic;
   signal cache_checking    : std_logic;
   signal cache_checking    : std_logic;
   signal cache_miss        : std_logic;
   signal cache_miss        : std_logic;
   signal cache_hit         : std_logic;
   signal cache_hit         : std_logic;
 
 
begin  --architecture
begin  --architecture
   write_enable <= '1' when cpu_byte_we /= "0000" else '0';
   write_enable <= '1' when cpu_byte_we /= "0000" else '0';
   mem_busy <= eth_pause or mem_pause_in;
   mem_busy <= eth_pause or mem_pause_in;
   cache_hit <= cache_checking and not cache_miss;
   cache_hit <= cache_checking and not cache_miss;
   cpu_pause <= (uart_write_busy and enable_uart and write_enable) or  --UART busy
   cpu_pause <= (uart_write_busy and enable_uart and write_enable) or  --UART busy
      cache_miss or                                                    --Cache wait
      cache_miss or                                                    --Cache wait
      (cpu_address(28) and not cache_hit and mem_busy);                --DDR or flash                                    --DDR in use
      (cpu_address(28) and not cache_hit and mem_busy);                --DDR or flash
   irq_status <= gpioA_in(31) & not gpioA_in(31) &
   irq_status <= gpioA_in(31) & not gpioA_in(31) &
                 irq_eth_send & irq_eth_rec &
                 irq_eth_send & irq_eth_rec &
                 counter_reg(18) & not counter_reg(18) &
                 counter_reg(18) & not counter_reg(18) &
                 not uart_write_busy & uart_data_avail;
                 not uart_write_busy & uart_data_avail;
   irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
   irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
Line 138... Line 138...
         data_w       => cpu_data_w,
         data_w       => cpu_data_w,
         data_r       => cpu_data_r,
         data_r       => cpu_data_r,
         mem_pause    => cpu_pause);
         mem_pause    => cpu_pause);
 
 
   opt_cache: if use_cache = '0' generate
   opt_cache: if use_cache = '0' generate
      cache_check <= '0';
      cache_access <= '0';
      cache_checking <= '0';
      cache_checking <= '0';
      cache_miss <= '0';
      cache_miss <= '0';
   end generate;
   end generate;
 
 
   opt_cache2: if use_cache = '1' generate
   opt_cache2: if use_cache = '1' generate
Line 156... Line 156...
         address_next   => address_next,
         address_next   => address_next,
         byte_we_next   => byte_we_next,
         byte_we_next   => byte_we_next,
         cpu_address    => cpu_address(31 downto 2),
         cpu_address    => cpu_address(31 downto 2),
         mem_busy       => mem_busy,
         mem_busy       => mem_busy,
 
 
         cache_check    => cache_check,    --Stage1: address_next in first 2MB DDR
         cache_access   => cache_access,    --access 4KB cache
         cache_checking => cache_checking, --Stage2
         cache_checking => cache_checking,  --checking if cache hit
         cache_miss     => cache_miss);    --Stage3
         cache_miss     => cache_miss);     --cache miss
   end generate; --opt_cache2
   end generate; --opt_cache2
 
 
   no_ddr_start <= not eth_pause and cache_checking;
   no_ddr_start <= not eth_pause and cache_checking;
   no_ddr_stop <= not eth_pause and cache_miss;
   no_ddr_stop <= not eth_pause and cache_miss;
   eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
   eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
Line 223... Line 223...
         end if;
         end if;
         counter_reg <= bv_inc(counter_reg);
         counter_reg <= bv_inc(counter_reg);
      end if;
      end if;
   end process;
   end process;
 
 
   ram_enable <= '1' when address_next(30 downto 28) = "000" or
   ram_proc: process(cache_access, cache_miss,
                  cache_check = '1' or cache_miss = '1' else '0';
                     address_next, cpu_address,
   ram_byte_we <= byte_we_next when cache_miss = '0' else "1111";
                     byte_we_next, cpu_data_w, data_read)
   ram_address(31 downto 13) <= ZERO(31 downto 13);
   begin
   ram_address(12 downto 2) <= (address_next(12) or cache_check) & address_next(11 downto 2)
      if cache_access = '1' then    --Check if cache hit or write through
            when cache_miss = '0' else
         ram_enable <= '1';
            '1' & cpu_address(11 downto 2);  --Update cache after cache miss
         ram_byte_we <= byte_we_next;
   ram_data_w <= cpu_data_w when cache_miss = '0' else data_read;
         ram_address(31 downto 2) <= ZERO(31 downto 16) &
 
            "0001" & address_next(11 downto 2);
 
         ram_data_w <= cpu_data_w;
 
      elsif cache_miss = '1' then  --Update cache after cache miss
 
         ram_enable <= '1';
 
         ram_byte_we <= "1111";
 
         ram_address(31 downto 2) <= ZERO(31 downto 16) &
 
            "0001" & cpu_address(11 downto 2);
 
         ram_data_w <= data_read;
 
      else                         --Normal non-cache access
 
         if address_next(30 downto 28) = "000" then
 
            ram_enable <= '1';
 
         else
 
            ram_enable <= '0';
 
         end if;
 
         ram_byte_we <= byte_we_next;
 
         ram_address(31 downto 2) <= address_next(31 downto 2);
 
         ram_data_w <= cpu_data_w;
 
      end if;
 
   end process;
 
 
   u2_ram: ram
   u2_ram: ram
      generic map (memory_type => memory_type)
      generic map (memory_type => memory_type)
      port map (
      port map (
         clk               => clk,
         clk               => clk,

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