| Line 10... |
Line 10... |
-- This entity divides the clock by two and interfaces to the
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-- This entity divides the clock by two and interfaces to the
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-- Xilinx Spartan-3E XC3S200FT256-4 FPGA with DDR.
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-- Xilinx Spartan-3E XC3S200FT256-4 FPGA with DDR.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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--use work.mlite_pack.all;
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--use work.mlite_pack.all;
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entity plasma_3e is
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entity plasma_3e is
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port(CLK_50MHZ : in std_logic;
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port(CLK_50MHZ : in std_logic;
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RS232_DCE_RXD : in std_logic;
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RS232_DCE_RXD : in std_logic;
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RS232_DCE_TXD : out std_logic;
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RS232_DCE_TXD : out std_logic;
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SD_CK_P : out std_logic; --clock_positive
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SD_CK_P : out std_logic; --DDR SDRAM clock_positive
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SD_CK_N : out std_logic; --clock_negative
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SD_CK_N : out std_logic; --clock_negative
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SD_CKE : out std_logic; --clock_enable
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SD_CKE : out std_logic; --clock_enable
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SD_BA : out std_logic_vector(1 downto 0); --bank_address
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SD_BA : out std_logic_vector(1 downto 0); --bank_address
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SD_A : out std_logic_vector(12 downto 0); --address(row or col)
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SD_A : out std_logic_vector(12 downto 0); --address(row or col)
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| Line 34... |
Line 36... |
SD_UDM : out std_logic; --upper_byte_enable
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SD_UDM : out std_logic; --upper_byte_enable
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SD_UDQS : inout std_logic; --upper_data_strobe
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SD_UDQS : inout std_logic; --upper_data_strobe
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SD_LDM : out std_logic; --low_byte_enable
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SD_LDM : out std_logic; --low_byte_enable
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SD_LDQS : inout std_logic; --low_data_strobe
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SD_LDQS : inout std_logic; --low_data_strobe
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E_MDC : out std_logic; --Ethernet PHY
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E_MDIO : inout std_logic; --management data in/out
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E_RX_CLK : in std_logic; --receive clock
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E_RX_DV : in std_logic; --data valid
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E_RXD : in std_logic_vector(3 downto 0);
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E_TX_CLK : in std_logic; --transmit clock
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E_TX_EN : out std_logic; --data valid
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E_TXD : out std_logic_vector(3 downto 0);
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SF_CE0 : out std_logic; --NOR flash
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SF_OE : out std_logic;
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SF_WE : out std_logic;
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SF_BYTE : out std_logic;
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SF_STS : in std_logic; --status
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SF_A : out std_logic_vector(24 downto 0);
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SF_D : inout std_logic_vector(15 downto 1);
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SPI_MISO : inout std_logic;
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VGA_VSYNC : out std_logic; --VGA port
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VGA_HSYNC : out std_logic;
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VGA_RED : out std_logic;
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VGA_GREEN : out std_logic;
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VGA_BLUE : out std_logic;
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PS2_CLK : in std_logic; --Keyboard
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PS2_DATA : in std_logic;
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LED : out std_logic_vector(7 downto 0);
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LED : out std_logic_vector(7 downto 0);
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ROT_CENTER : in std_logic;
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ROT_CENTER : in std_logic;
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ROT_A : in std_logic;
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ROT_A : in std_logic;
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ROT_B : in std_logic;
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ROT_B : in std_logic;
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BTN_EAST : in std_logic;
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BTN_EAST : in std_logic;
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| Line 50... |
Line 79... |
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architecture logic of plasma_3e is
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architecture logic of plasma_3e is
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component plasma
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component plasma
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generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
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generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
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log_file : string := "UNUSED");
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log_file : string := "UNUSED";
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ethernet : std_logic := '0');
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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uart_write : out std_logic;
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uart_write : out std_logic;
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uart_read : in std_logic;
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uart_read : in std_logic;
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| Line 100... |
Line 130... |
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signal clk_reg : std_logic;
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signal clk_reg : std_logic;
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signal address : std_logic_vector(31 downto 2);
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signal address : std_logic_vector(31 downto 2);
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signal data_write : std_logic_vector(31 downto 0);
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signal data_write : std_logic_vector(31 downto 0);
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signal data_read : std_logic_vector(31 downto 0);
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signal data_read : std_logic_vector(31 downto 0);
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signal data_r_ddr : std_logic_vector(31 downto 0);
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signal byte_we : std_logic_vector(3 downto 0);
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signal byte_we : std_logic_vector(3 downto 0);
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signal write_enable : std_logic;
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signal pause_ddr : std_logic;
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signal pause : std_logic;
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signal pause : std_logic;
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signal active : std_logic;
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signal ddr_active : std_logic;
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signal flash_active : std_logic;
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signal flash_cnt : std_logic_vector(1 downto 0);
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signal flash_we : std_logic;
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signal reset : std_logic;
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signal reset : std_logic;
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signal gpio0_out : std_logic_vector(31 downto 0);
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signal gpio0_out : std_logic_vector(31 downto 0);
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signal gpio0_in : std_logic_vector(31 downto 0);
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signal gpio0_in : std_logic_vector(31 downto 0);
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begin --architecture
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begin --architecture
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| Line 119... |
Line 155... |
clk_reg <= not clk_reg;
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clk_reg <= not clk_reg;
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end if;
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end if;
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end process; --clk_div
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end process; --clk_div
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reset <= ROT_CENTER;
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reset <= ROT_CENTER;
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E_TX_EN <= gpio0_out(28); --Ethernet
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E_TXD <= gpio0_out(27 downto 24);
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E_MDC <= gpio0_out(23);
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E_MDIO <= gpio0_out(21) when gpio0_out(22) = '1' else 'Z';
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VGA_VSYNC <= gpio0_out(20);
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VGA_HSYNC <= gpio0_out(19);
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VGA_RED <= gpio0_out(18);
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VGA_GREEN <= gpio0_out(17);
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VGA_BLUE <= gpio0_out(16);
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LED <= gpio0_out(7 downto 0);
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LED <= gpio0_out(7 downto 0);
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gpio0_in(31 downto 10) <= (others => '0');
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gpio0_in(31 downto 21) <= (others => '0');
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gpio0_in(20 downto 13) <= E_RX_CLK & E_RX_DV & E_RXD & E_TX_CLK & E_MDIO;
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gpio0_in(12 downto 10) <= SF_STS & PS2_CLK & PS2_DATA;
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gpio0_in(9 downto 0) <= ROT_A & ROT_B & BTN_EAST & BTN_NORTH &
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gpio0_in(9 downto 0) <= ROT_A & ROT_B & BTN_EAST & BTN_NORTH &
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BTN_SOUTH & BTN_WEST & SW;
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BTN_SOUTH & BTN_WEST & SW;
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active <= '1' when address(31 downto 28) = "0001" else '0';
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ddr_active <= '1' when address(31 downto 28) = "0001" else '0';
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flash_active <= '1' when address(31 downto 28) = "0011" else '0';
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write_enable <= '1' when byte_we /= "0000" else '0';
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u1_plama: plasma
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u1_plama: plasma
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generic map (memory_type => "XILINX_16X",
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generic map (memory_type => "XILINX_16X",
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log_file => "UNUSED")
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log_file => "UNUSED",
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--generic map (memory_type => "DUAL_PORT",
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ethernet => '1')
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-- log_file => "output2.txt")
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--generic map (memory_type => "DUAL_PORT_",
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-- log_file => "output2.txt",
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-- ethernet => '1')
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PORT MAP (
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PORT MAP (
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clk => clk_reg,
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clk => clk_reg,
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reset => reset,
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reset => reset,
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uart_write => RS232_DCE_TXD,
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uart_write => RS232_DCE_TXD,
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uart_read => RS232_DCE_RXD,
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uart_read => RS232_DCE_RXD,
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| Line 154... |
Line 205... |
reset_in => reset,
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reset_in => reset,
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address => address(25 downto 2),
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address => address(25 downto 2),
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byte_we => byte_we,
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byte_we => byte_we,
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data_w => data_write,
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data_w => data_write,
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data_r => data_read,
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data_r => data_r_ddr,
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active => active,
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active => ddr_active,
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pause => pause,
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pause => pause_ddr,
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SD_CK_P => SD_CK_P, --clock_positive
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SD_CK_P => SD_CK_P, --clock_positive
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SD_CK_N => SD_CK_N, --clock_negative
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SD_CK_N => SD_CK_N, --clock_negative
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SD_CKE => SD_CKE, --clock_enable
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SD_CKE => SD_CKE, --clock_enable
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| Line 175... |
Line 226... |
SD_UDM => SD_UDM, --upper_byte_enable
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SD_UDM => SD_UDM, --upper_byte_enable
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SD_UDQS => SD_UDQS, --upper_data_strobe
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SD_UDQS => SD_UDQS, --upper_data_strobe
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SD_LDM => SD_LDM, --low_byte_enable
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SD_LDM => SD_LDM, --low_byte_enable
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SD_LDQS => SD_LDQS); --low_data_strobe
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SD_LDQS => SD_LDQS); --low_data_strobe
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--Flash control (only lower 16-bit data lines connected)
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flash_ctrl: process(reset, clk_reg, flash_active, write_enable,
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flash_cnt, pause_ddr)
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begin
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if reset = '1' then
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flash_cnt <= "00";
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flash_we <= '1';
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elsif rising_edge(clk_reg) then
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if flash_active = '0' then
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flash_cnt <= "00";
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flash_we <= '1';
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else
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if write_enable = '1' and flash_cnt(1) = '0' then
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flash_we <= '0';
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else
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flash_we <= '1';
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end if;
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if flash_cnt /= "11" then
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flash_cnt <= flash_cnt + 1;
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end if;
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end if;
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end if; --rising_edge(clk_reg)
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if pause_ddr = '1' or (flash_active = '1' and flash_cnt /= "11") then
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pause <= '1';
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else
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pause <= '0';
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end if;
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end process; --flash_ctrl
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SF_CE0 <= not flash_active;
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SF_OE <= write_enable or not flash_active;
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SF_WE <= flash_we;
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SF_BYTE <= '1'; --16-bit access
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SF_A <= address(25 downto 2) & '0';
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SF_D <= data_write(15 downto 1) when
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flash_active = '1' and write_enable = '1'
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else "ZZZZZZZZZZZZZZZ";
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SPI_MISO <= data_write(0) when
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flash_active = '1' and write_enable = '1'
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else 'Z';
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data_read(31 downto 16) <= data_r_ddr(31 downto 16);
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data_read(15 downto 0) <= data_r_ddr(15 downto 0) when flash_active = '0'
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else SF_D & SPI_MISO;
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end; --architecture logic
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end; --architecture logic
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No newline at end of file
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No newline at end of file
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