| Line 90... |
Line 90... |
end generate; --generic_ram
|
end generate; --generic_ram
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altera_ram:
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altera_ram:
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if memory_type = "ALTERA_LPM" generate
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if memory_type = "ALTERA_LPM" generate
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signal byte_we : std_logic_vector(3 downto 0);
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byte_we <= write_byte_enable when enable = '1' else "0000";
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lpm_ram_io_component0 : lpm_ram_dq
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lpm_ram_io_component0 : lpm_ram_dq
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GENERIC MAP (
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GENERIC MAP (
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intended_device_family => "UNUSED",
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intended_device_family => "UNUSED",
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lpm_width => 8,
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lpm_width => 8,
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lpm_widthad => ADDRESS_WIDTH-2,
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lpm_widthad => ADDRESS_WIDTH-2,
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| Line 105... |
Line 107... |
lpm_type => "LPM_RAM_DQ")
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lpm_type => "LPM_RAM_DQ")
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PORT MAP (
|
PORT MAP (
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data => data_write(31 downto 24),
|
data => data_write(31 downto 24),
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address => address(ADDRESS_WIDTH-1 downto 2),
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address => address(ADDRESS_WIDTH-1 downto 2),
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inclock => clk,
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inclock => clk,
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we => write_byte_enable(3),
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we => byte_we(3),
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q => data_read(31 downto 24));
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q => data_read(31 downto 24));
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lpm_ram_io_component1 : lpm_ram_dq
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lpm_ram_io_component1 : lpm_ram_dq
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GENERIC MAP (
|
GENERIC MAP (
|
intended_device_family => "UNUSED",
|
intended_device_family => "UNUSED",
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| Line 123... |
Line 125... |
lpm_type => "LPM_RAM_DQ")
|
lpm_type => "LPM_RAM_DQ")
|
PORT MAP (
|
PORT MAP (
|
data => data_write(23 downto 16),
|
data => data_write(23 downto 16),
|
address => address(ADDRESS_WIDTH-1 downto 2),
|
address => address(ADDRESS_WIDTH-1 downto 2),
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inclock => clk,
|
inclock => clk,
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we => write_byte_enable(2),
|
we => byte_we(2),
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q => data_read(23 downto 16));
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q => data_read(23 downto 16));
|
|
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lpm_ram_io_component2 : lpm_ram_dq
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lpm_ram_io_component2 : lpm_ram_dq
|
GENERIC MAP (
|
GENERIC MAP (
|
intended_device_family => "UNUSED",
|
intended_device_family => "UNUSED",
|
| Line 141... |
Line 143... |
lpm_type => "LPM_RAM_DQ")
|
lpm_type => "LPM_RAM_DQ")
|
PORT MAP (
|
PORT MAP (
|
data => data_write(15 downto 8),
|
data => data_write(15 downto 8),
|
address => address(ADDRESS_WIDTH-1 downto 2),
|
address => address(ADDRESS_WIDTH-1 downto 2),
|
inclock => clk,
|
inclock => clk,
|
we => write_byte_enable(1),
|
we => byte_we(1),
|
q => data_read(15 downto 8));
|
q => data_read(15 downto 8));
|
|
|
lpm_ram_io_component3 : lpm_ram_dq
|
lpm_ram_io_component3 : lpm_ram_dq
|
GENERIC MAP (
|
GENERIC MAP (
|
intended_device_family => "UNUSED",
|
intended_device_family => "UNUSED",
|
| Line 159... |
Line 161... |
lpm_type => "LPM_RAM_DQ")
|
lpm_type => "LPM_RAM_DQ")
|
PORT MAP (
|
PORT MAP (
|
data => data_write(7 downto 0),
|
data => data_write(7 downto 0),
|
address => address(ADDRESS_WIDTH-1 downto 2),
|
address => address(ADDRESS_WIDTH-1 downto 2),
|
inclock => clk,
|
inclock => clk,
|
we => write_byte_enable(0),
|
we => byte_we(0),
|
q => data_read(7 downto 0));
|
q => data_read(7 downto 0));
|
|
|
end generate; --altera_ram
|
end generate; --altera_ram
|
|
|
|
|
