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[/] [plasma/] [trunk/] [vhdl/] [ram.vhd] - Diff between revs 55 and 85

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Rev 55 Rev 85
Line 13... Line 13...
---------------------------------------------------------------------
---------------------------------------------------------------------
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
 
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use std.textio.all;
 
 
use ieee.std_logic_unsigned.all;
 
use work.mlite_pack.all;
use work.mlite_pack.all;
 
 
entity ram is
entity ram is
   generic(memory_type : string := "GENERIC");
   generic(memory_type : string := "GENERIC");
   port(clk          : in std_logic;
   port(clk          : in std_logic;
Line 37... Line 36...
   signal mem_sel           : std_logic;
   signal mem_sel           : std_logic;
   signal read_enable       : std_logic;
   signal read_enable       : std_logic;
   signal write_byte_enable : std_logic_vector(3 downto 0);
   signal write_byte_enable : std_logic_vector(3 downto 0);
begin
begin
   clk_inv <= not clk;
   clk_inv <= not clk;
   mem_sel <= '1' when mem_address(30 downto 16) = ZERO(30 downto 16) else
   mem_sel <= '1' when mem_address(30 downto ADDRESS_WIDTH) = ZERO(30 downto ADDRESS_WIDTH) else
              '0';
              '0';
   read_enable <= mem_sel and not mem_write;
   read_enable <= mem_sel and not mem_write;
   write_byte_enable <= mem_byte_sel when mem_sel = '1' else
   write_byte_enable <= mem_byte_sel when mem_sel = '1' else
                        "0000";
                        "0000";
 
 
Line 66... Line 65...
            readline(load_file, hex_file_line);
            readline(load_file, hex_file_line);
            hread(hex_file_line, data);
            hread(hex_file_line, data);
            storage(index) := data;
            storage(index) := data;
            index := index + 1;
            index := index + 1;
         end loop;
         end loop;
         --assert false report "done reading code" severity note;
 
      end if;
      end if;
 
 
      index := conv_integer(mem_address(ADDRESS_WIDTH-1 downto 2));
      index := conv_integer(mem_address(ADDRESS_WIDTH-1 downto 2));
      data := storage(index);
      data := storage(index);
 
 

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