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[/] [plasma/] [trunk/] [vhdl/] [reg_bank.vhd] - Diff between revs 352 and 365
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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--library UNISIM; --May need to uncomment for ModelSim
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--use UNISIM.vcomponents.all; --May need to uncomment for ModelSim
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entity reg_bank is
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entity reg_bank is
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generic(memory_type : string := "XILINX_16X");
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generic(memory_type : string := "XILINX_16X");
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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