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[/] [plasma/] [trunk/] [vhdl/] [reg_bank.vhd] - Diff between revs 365 and 376
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| Rev 365 |
Rev 376 |
| Line 252... |
Line 252... |
-- the read address signal can be sent from the mem_ctrl block.
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-- the read address signal can be sent from the mem_ctrl block.
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-- This solution also delays the how fast the registers are read so the
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-- This solution also delays the how fast the registers are read so the
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-- maximum clock speed is cut in half (12.5 MHz instead of 25 MHz).
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-- maximum clock speed is cut in half (12.5 MHz instead of 25 MHz).
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clk_delayed <= not clk; --Could be delayed by 1/4 clock cycle instead
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clk_delayed <= not clk; --Could be delayed by 1/4 clock cycle instead
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dpram_bypass: process(clk, addr_write, reg_dest_new)
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dpram_bypass: process(clk, addr_write, reg_dest_new, write_enable)
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begin
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begin
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if rising_edge(clk) and write_enable = '1' then
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if rising_edge(clk) and write_enable = '1' then
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addr_reg <= addr_write;
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addr_reg <= addr_write;
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data_reg <= reg_dest_new;
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data_reg <= reg_dest_new;
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end if;
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end if;
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