| Line 235... |
Line 235... |
data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
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data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
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end generate; --xilinx_16x1d
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end generate; --xilinx_16x1d
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-- Option #4
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-- Option #4
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-- RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port
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-- distributed RAM for 5-LUT Xilinx FPGAs such as Virtex-5
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-- From library UNISIM; use UNISIM.vcomponents.all;
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xilinx_32x1d:
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if memory_type = "XILINX_32X" generate
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signal no_connect : std_logic_vector(63 downto 0);
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begin
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reg_loop: for i in 0 to 31 generate
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begin
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--Read port 1
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reg_bit1 : RAM32X1D
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port map (
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WCLK => clk, -- Port A write clock input
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WE => write_enable, -- Port A write enable input
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A0 => addr_write(0), -- Port A address[0] input bit
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A1 => addr_write(1), -- Port A address[1] input bit
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A2 => addr_write(2), -- Port A address[2] input bit
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A3 => addr_write(3), -- Port A address[3] input bit
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A4 => addr_write(4), -- Port A address[4] input bit
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D => reg_dest_new(i), -- Port A 1-bit data input
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DPRA0 => addr_read1(0), -- Port B address[0] input bit
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DPRA1 => addr_read1(1), -- Port B address[1] input bit
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DPRA2 => addr_read1(2), -- Port B address[2] input bit
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DPRA3 => addr_read1(3), -- Port B address[3] input bit
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DPRA4 => addr_read1(4), -- Port B address[4] input bit
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DPO => data_out1(i), -- Port B 1-bit data output
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SPO => no_connect(i) -- Port A 1-bit data output
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);
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--Read port 2
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reg_bit2 : RAM32X1D
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port map (
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WCLK => clk, -- Port A write clock input
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WE => write_enable, -- Port A write enable input
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A0 => addr_write(0), -- Port A address[0] input bit
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A1 => addr_write(1), -- Port A address[1] input bit
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A2 => addr_write(2), -- Port A address[2] input bit
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A3 => addr_write(3), -- Port A address[3] input bit
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A4 => addr_write(4), -- Port A address[4] input bit
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D => reg_dest_new(i), -- Port A 1-bit data input
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DPRA0 => addr_read2(0), -- Port B address[0] input bit
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DPRA1 => addr_read2(1), -- Port B address[1] input bit
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DPRA2 => addr_read2(2), -- Port B address[2] input bit
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DPRA3 => addr_read2(3), -- Port B address[3] input bit
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DPRA4 => addr_read2(4), -- Port B address[4] input bit
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DPO => data_out2(i), -- Port B 1-bit data output
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SPO => no_connect(32+i) -- Port A 1-bit data output
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);
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end generate; --reg_loop
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end generate; --xilinx_32x1d
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|
|
|
|
-- Option #5
|
-- Altera LPM_RAM_DP
|
-- Altera LPM_RAM_DP
|
altera_mem:
|
altera_mem:
|
if memory_type = "ALTERA_LPM" generate
|
if memory_type = "ALTERA_LPM" generate
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signal clk_delayed : std_logic;
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signal clk_delayed : std_logic;
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signal addr_reg : std_logic_vector(4 downto 0);
|
signal addr_reg : std_logic_vector(4 downto 0);
|
