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Line 37... |
signal bits_write_reg : std_logic_vector(3 downto 0);
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signal bits_write_reg : std_logic_vector(3 downto 0);
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signal data_write_reg : std_logic_vector(8 downto 0);
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signal data_write_reg : std_logic_vector(8 downto 0);
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signal delay_read_reg : std_logic_vector(9 downto 0);
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signal delay_read_reg : std_logic_vector(9 downto 0);
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signal bits_read_reg : std_logic_vector(3 downto 0);
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signal bits_read_reg : std_logic_vector(3 downto 0);
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signal data_read_reg : std_logic_vector(7 downto 0);
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signal data_read_reg : std_logic_vector(7 downto 0);
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signal data_save_reg : std_logic_vector(8 downto 0);
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signal data_save_reg : std_logic_vector(17 downto 0);
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signal busy_write_sig : std_logic;
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signal busy_write_sig : std_logic;
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signal read_value_reg : std_logic_vector(7 downto 0);
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signal read_value_reg : std_logic_vector(7 downto 0);
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signal uart_read2 : std_logic;
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signal uart_read2 : std_logic;
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begin
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begin
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Line 65... |
delay_write_reg <= ZERO(9 downto 0);
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delay_write_reg <= ZERO(9 downto 0);
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read_value_reg <= ONES(7 downto 0);
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read_value_reg <= ONES(7 downto 0);
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data_read_reg <= ZERO(7 downto 0);
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data_read_reg <= ZERO(7 downto 0);
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bits_read_reg <= "0000";
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bits_read_reg <= "0000";
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delay_read_reg <= ZERO(9 downto 0);
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delay_read_reg <= ZERO(9 downto 0);
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data_save_reg <= ZERO(8 downto 0);
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data_save_reg <= ZERO(17 downto 0);
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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--Write UART
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--Write UART
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if bits_write_reg = "0000" then --nothing left to write?
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if bits_write_reg = "0000" then --nothing left to write?
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if enable_write = '1' then
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if enable_write = '1' then
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Line 112... |
end if;
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end if;
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else
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else
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delay_read_reg <= delay_read_reg - 1; --delay
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delay_read_reg <= delay_read_reg - 1; --delay
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end if;
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end if;
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--Control character buffer
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if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
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if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
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data_save_reg <= '1' & data_read_reg;
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if data_save_reg(8) = '0' or
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(enable_read = '1' and data_save_reg(17) = '0') then
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--Empty buffer
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data_save_reg(8 downto 0) <= '1' & data_read_reg;
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else
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--Second character in buffer
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data_save_reg(17 downto 9) <= '1' & data_read_reg;
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if enable_read = '1' then
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data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
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end if;
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end if;
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elsif enable_read = '1' then
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elsif enable_read = '1' then
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data_save_reg(8) <= '0'; --data_available
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data_save_reg(17) <= '0'; --data_available
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data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
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end if;
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end if;
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end if; --rising_edge(clk)
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end if; --rising_edge(clk)
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uart_write <= data_write_reg(0);
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uart_write <= data_write_reg(0);
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if bits_write_reg /= "0000"
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if bits_write_reg /= "0000"
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