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Line 18... |
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity uart is
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entity uart is
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generic(save_file_name : string);
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generic(log_file : string := "UNUSED");
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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uart_sel : in std_logic;
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uart_sel : in std_logic;
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data : in std_logic_vector(7 downto 0);
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data : in std_logic_vector(7 downto 0);
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read_pin : in std_logic;
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uart_read : in std_logic;
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write_pin : out std_logic;
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uart_write : out std_logic;
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pause : out std_logic);
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pause : out std_logic);
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end; --entity ram
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end; --entity ram
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architecture logic of uart is
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architecture logic of uart is
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signal uart_data_reg : std_logic_vector(8 downto 0);
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signal uart_data_reg : std_logic_vector(8 downto 0);
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signal uart_bits_reg : std_logic_vector(3 downto 0);
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signal uart_bits_reg : std_logic_vector(3 downto 0);
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signal uart_div_reg : std_logic_vector(7 downto 0);
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signal uart_div_reg : std_logic_vector(7 downto 0);
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begin
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begin
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uart_proc: process(clk, reset, uart_sel, data,
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uart_proc: process(clk, reset, uart_sel, data,
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uart_data_reg, uart_bits_reg, uart_div_reg)
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uart_data_reg, uart_bits_reg, uart_div_reg)
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file store_file : text is out save_file_name;
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variable hex_file_line : line;
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variable c : character;
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variable index : natural;
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variable line_length : natural := 0;
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variable uart_data_next : std_logic_vector(8 downto 0);
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variable uart_data_next : std_logic_vector(8 downto 0);
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variable uart_bits_next : std_logic_vector(3 downto 0);
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variable uart_bits_next : std_logic_vector(3 downto 0);
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variable uart_div_next : std_logic_vector(7 downto 0);
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variable uart_div_next : std_logic_vector(7 downto 0);
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begin
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begin
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uart_data_next := uart_data_reg;
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uart_data_next := uart_data_reg;
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uart_bits_next := uart_bits_reg;
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uart_bits_next := uart_bits_reg;
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uart_div_next := uart_div_reg;
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uart_div_next := uart_div_reg;
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if uart_bits_reg = "0000" and uart_sel = '1' then
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if uart_bits_reg = "0000" and uart_sel = '1' then
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uart_data_next := '1' & data;
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uart_data_next := data & '0';
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uart_bits_next := "1001";
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uart_bits_next := "1010";
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uart_div_next := ZERO(7 downto 0);
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uart_div_next := ZERO(7 downto 0);
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--"10001100"
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elsif uart_bits_reg /= "0000" and
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elsif uart_bits_reg /= "0000" and uart_div_reg = "00000100" then
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((log_file /= "UNUSED" and uart_div_reg = "00000010") or
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uart_data_next := uart_data_reg(7 downto 0) & '0';
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(log_file = "UNUSED" and uart_div_reg = "10001100")) then
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uart_data_next := '1' & uart_data_reg(8 downto 1);
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uart_bits_next := uart_bits_reg - 1;
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uart_bits_next := uart_bits_reg - 1;
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uart_div_next := ZERO(7 downto 0);
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uart_div_next := ZERO(7 downto 0);
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else
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else
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uart_div_next := uart_div_reg + 1;
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uart_div_next := uart_div_reg + 1;
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end if;
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end if;
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if reset = '1' then
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if reset = '1' then
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uart_data_next := ZERO(8 downto 0);
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uart_data_next := ONES(8 downto 0);
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uart_bits_next := "0000";
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uart_bits_next := "0000";
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uart_div_next := ZERO(7 downto 0);
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uart_div_next := ZERO(7 downto 0);
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end if;
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end if;
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if rising_edge(clk) then
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if rising_edge(clk) then
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uart_data_reg <= uart_data_next;
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uart_bits_reg <= uart_bits_next;
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uart_div_reg <= uart_div_next;
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end if;
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uart_write <= uart_data_reg(0);
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if uart_bits_reg = ZERO(7 downto 0) or uart_sel = '1' then
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pause <= '0';
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elsif log_file = "UNUSED" then
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pause <= '1';
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else
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-- pause <= '1';
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pause <= '0';
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end if;
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end process;
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uart_logger:
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if log_file /= "UNUSED" generate
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uart_proc: process(clk, uart_sel, data)
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file store_file : text is out log_file;
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variable hex_file_line : line;
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variable c : character;
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variable index : natural;
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variable line_length : natural := 0;
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begin
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if rising_edge(clk) then
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if uart_sel = '1' then
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if uart_sel = '1' then
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-- Debug log file
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index := conv_integer(data(6 downto 0));
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index := conv_integer(data(6 downto 0));
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if index /= 10 then
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if index /= 10 then
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c := character'val(index);
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c := character'val(index);
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write(hex_file_line, c);
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write(hex_file_line, c);
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line_length := line_length + 1;
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line_length := line_length + 1;
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end if;
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end if;
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if index = 10 or line_length >= 72 then
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if index = 10 or line_length >= 72 then
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writeline(store_file, hex_file_line);
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writeline(store_file, hex_file_line);
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line_length := 0;
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line_length := 0;
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end if;
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end if;
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end if;
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end if; --uart_sel
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end if; --rising_edge(clk)
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uart_data_reg <= uart_data_next;
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end process; --uart_proc
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uart_bits_reg <= uart_bits_next;
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end generate; --uart_logger
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uart_div_reg <= uart_div_next;
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end if;
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write_pin <= uart_data_reg(8);
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if uart_bits_reg = ZERO(7 downto 0) or uart_sel = '1' then
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-- pause <= '0';
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else
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-- pause <= '1';
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end if;
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pause <= '0';
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end process;
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end; --architecture logic
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end; --architecture logic
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