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----------------------------------------------------------------------
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---- ----
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---- PlTbUtils Example DUT ----
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---- ----
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---- This file is part of the PlTbUtils project ----
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---- http://opencores.org/project,pltbutils ----
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---- ----
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---- Description: ----
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---- PlTbUtils is a collection of functions, procedures and ----
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---- components for easily creating stimuli and checking response ----
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---- in automatic self-checking testbenches. ----
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---- ----
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---- This file is an example component for use as DUT ----
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---- (Device Under Test) in tb_example.vhd, which demonstrates ----
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---- how PlTbUtils can be used. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Per Larsson, pela@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dut_example is
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generic (
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G_WIDTH : integer := 8;
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G_DISABLE_BUGS : integer range 0 to 1 := 1
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);
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port (
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clk_i : in std_logic;
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rst_i : in std_logic;
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carry_i : in std_logic;
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x_i : in std_logic_vector(G_WIDTH-1 downto 0);
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y_i : in std_logic_vector(G_WIDTH-1 downto 0);
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sum_o : out std_logic_vector(G_WIDTH-1 downto 0);
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carry_o : out std_logic
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);
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end entity dut_example;
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architecture rtl of dut_example is
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signal x : unsigned(G_WIDTH downto 0);
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signal y : unsigned(G_WIDTH downto 0);
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signal c : unsigned(G_WIDTH downto 0);
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signal sum : unsigned(G_WIDTH downto 0);
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begin
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x <= resize(unsigned(x_i), G_WIDTH+1);
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y <= resize(unsigned(y_i), G_WIDTH+1);
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c <= resize(unsigned(std_logic_vector'('0' & carry_i)), G_WIDTH+1);
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p_sum : process(clk_i)
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begin
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if rising_edge(clk_i) then
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if rst_i = '1' then
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sum <= (others => '0');
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else
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if G_DISABLE_BUGS = 1 then
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sum <= x + y + c;
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else
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sum <= x + y;
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end if;
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end if;
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end if;
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end process;
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sum_o <= std_logic_vector(sum(sum'high-1 downto 0));
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carry_o <= sum(sum'high);
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end architecture rtl;
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