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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- PlTbUtils Example Testbench ----
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---- PlTbUtils Testbench Example 2 ----
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---- ----
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---- ----
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---- This file is part of the PlTbUtils project ----
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---- This file is part of the PlTbUtils project ----
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---- http://opencores.org/project,pltbutils ----
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---- http://opencores.org/project,pltbutils ----
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---- ----
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---- ----
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---- Description: ----
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---- Description: ----
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.pltbutils_func_pkg.all;
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use work.pltbutils_func_pkg.all;
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use work.pltbutils_comp_pkg.all;
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use work.pltbutils_comp_pkg.all;
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entity tb_example is
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entity tb_example2 is
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generic (
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generic (
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G_WIDTH : integer := 8;
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G_WIDTH : integer := 8;
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G_CLK_PERIOD : time := 10 ns;
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G_CLK_PERIOD : time := 10 ns;
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G_DISABLE_BUGS : integer range 0 to 1 := 0
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G_DISABLE_BUGS : integer range 0 to 1 := 0
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);
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);
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end entity tb_example;
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end entity tb_example2;
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architecture bhv of tb_example is
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architecture bhv of tb_example2 is
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-- Simulation status- and control signals
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-- Simulation status- and control signals
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-- for accessing .stop_sim and for viewing in waveform window
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-- for accessing .stop_sim and for viewing in waveform window
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signal pltbs : pltbs_t := C_PLTBS_INIT;
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signal pltbs : pltbs_t := C_PLTBS_INIT;
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port map(
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port map(
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clk_o => clk,
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clk_o => clk,
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stop_sim_i => pltbs.stop_sim
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stop_sim_i => pltbs.stop_sim
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);
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);
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tc0 : entity work.tc_example
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tc0 : entity work.tc_example2
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generic map (
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generic map (
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G_WIDTH => G_WIDTH,
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G_WIDTH => G_WIDTH,
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G_DISABLE_BUGS => G_DISABLE_BUGS
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G_DISABLE_BUGS => G_DISABLE_BUGS
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)
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)
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port map(
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port map(
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