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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- PlTbUtils Example Testcase Entity for Template Testbench ----
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---- PlTbUtils Testcase Entity for Template Testbench ----
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---- ----
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---- ----
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---- This file is part of the PlTbUtils project ----
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---- This file is part of the PlTbUtils project ----
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---- http://opencores.org/project,pltbutils ----
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---- http://opencores.org/project,pltbutils ----
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---- ----
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---- ----
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---- Description: ----
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---- Description: ----
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---- ----
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---- ----
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---- This file is a template, which can be used as a base when ----
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---- This file is a template, which can be used as a base when ----
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---- testbenches which use PlTbUtils. ----
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---- testbenches which use PlTbUtils. ----
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---- Copy this file to your preferred location and rename the ----
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---- Copy this file to your preferred location and rename the ----
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---- copied file and its contents, by replacing the word ----
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---- copied file and its contents, by replacing the word ----
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---- "template" with a name for your design. ----
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---- "templateXX" with a name for your design. ----
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---- Also remove informative comments enclosed in < ... > . ----
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---- Also remove informative comments enclosed in < ... > . ----
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---- ----
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---- ----
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---- ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- - ----
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---- - ----
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.pltbutils_func_pkg.all;
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use work.pltbutils_func_pkg.all;
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entity tc_template is
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entity tc_template2 is
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generic (
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generic (
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-- < Template info: add generics here if needed, or remove the generic block >
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-- < Template info: add generics here if needed, or remove the generic block >
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);
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);
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port (
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port (
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pltbs : out pltbs_t;
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pltbs : out pltbs_t;
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-- < Inputs on the DUT should be outputs here, >
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-- < Inputs on the DUT should be outputs here, >
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-- < and vice versa. >
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-- < and vice versa. >
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-- < Exception: clocks are inputs both on DUT >
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-- < Exception: clocks are inputs both on DUT >
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-- < and here. >
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-- < and here. >
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);
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);
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end entity tc_template;
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end entity tc_template2;
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No newline at end of file
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