| Line 20... |
Line 20... |
---- Author(s): ----
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---- Author(s): ----
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---- - Per Larsson, pela@opencores.org ----
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---- - Per Larsson, pela@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2013-2014 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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| Line 46... |
Line 46... |
---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use work.txt_util.all;
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use work.pltbutils_func_pkg.all;
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use work.pltbutils_func_pkg.all;
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use work.pltbutils_comp_pkg.all;
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use work.pltbutils_comp_pkg.all;
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|
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entity tb_example is
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entity tb_example is
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generic (
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generic (
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| Line 62... |
Line 60... |
end entity tb_example;
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end entity tb_example;
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architecture bhv of tb_example is
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architecture bhv of tb_example is
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|
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-- Simulation status- and control signals
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-- Simulation status- and control signals
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signal test_num : integer;
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-- for accessing .stop_sim and for viewing in waveform window
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-- VHDL-1993:
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signal pltbs : pltbs_t := C_PLTBS_INIT;
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--signal test_name : string(pltbutils_test_name'range);
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--signal info : string(pltbutils_info'range);
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-- VHDL-2002:
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signal test_name : string(pltbutils_sc.test_name'range);
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signal info : string(pltbutils_sc.info'range);
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signal checks : integer;
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signal errors : integer;
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signal stop_sim : std_logic;
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-- DUT stimuli and response signals
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-- DUT stimuli and response signals
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signal clk : std_logic;
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signal clk : std_logic;
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signal rst : std_logic;
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signal rst : std_logic;
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signal carry_in : std_logic;
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signal carry_in : std_logic;
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| Line 85... |
Line 74... |
signal sum : std_logic_vector(G_WIDTH-1 downto 0);
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signal sum : std_logic_vector(G_WIDTH-1 downto 0);
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signal carry_out : std_logic;
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signal carry_out : std_logic;
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|
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begin
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begin
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|
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-- Simulation status and control for viewing in waveform window
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-- VHDL-1993:
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--test_num <= pltbutils_test_num;
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--test_name <= pltbutils_test_name;
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--checks <= pltbutils_chk_cnt;
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--errors <= pltbutils_err_cnt;
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-- VHDL-2002:
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test_num <= pltbutils_sc.test_num;
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test_name <= pltbutils_sc.test_name;
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info <= pltbutils_sc.info;
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checks <= pltbutils_sc.chk_cnt;
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errors <= pltbutils_sc.err_cnt;
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stop_sim <= pltbutils_sc.stop_sim;
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dut0 : entity work.dut_example
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dut0 : entity work.dut_example
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generic map (
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generic map (
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G_WIDTH => G_WIDTH,
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G_WIDTH => G_WIDTH,
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G_DISABLE_BUGS => G_DISABLE_BUGS
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G_DISABLE_BUGS => G_DISABLE_BUGS
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)
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)
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| Line 121... |
Line 95... |
generic map(
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generic map(
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G_PERIOD => G_CLK_PERIOD
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G_PERIOD => G_CLK_PERIOD
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)
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)
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port map(
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port map(
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clk_o => clk,
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clk_o => clk,
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stop_sim_i => stop_sim
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stop_sim_i => pltbs.stop_sim
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);
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);
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|
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tc0 : entity work.tc_example
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tc0 : entity work.tc_example
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generic map (
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generic map (
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G_WIDTH => G_WIDTH,
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G_WIDTH => G_WIDTH,
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G_DISABLE_BUGS => G_DISABLE_BUGS
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G_DISABLE_BUGS => G_DISABLE_BUGS
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)
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)
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port map(
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port map(
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pltbs => pltbs,
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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carry_in => carry_in,
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carry_in => carry_in,
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x => x,
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x => x,
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y => y,
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y => y,
|
