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Subversion Repositories pltbutils

[/] [pltbutils/] [branches/] [dev_beta0002/] [examples/] [vhdl/] [tb_example2/] [tc_example2.vhd] - Diff between revs 63 and 65

Rev 63	Rev 65
Line 48...	Line 48...
`----------------------------------------------------------------------`	`----------------------------------------------------------------------`
`library ieee;`	`library ieee;`
`use ieee.std_logic_1164.all;`	`use ieee.std_logic_1164.all;`
`use work.pltbutils_func_pkg.all;`	`use work.pltbutils_func_pkg.all;`

`entity tc_example is`	`entity tc_example2 is`
`generic (`	`generic (`
`G_WIDTH : integer := 8;`	`G_WIDTH : integer := 8;`
`G_DISABLE_BUGS : integer range 0 to 1 := 0`	`G_DISABLE_BUGS : integer range 0 to 1 := 0`
`);`	`);`
`port (`	`port (`
Line 63...	Line 63...
`x : out std_logic_vector(G_WIDTH-1 downto 0);`	`x : out std_logic_vector(G_WIDTH-1 downto 0);`
`y : out std_logic_vector(G_WIDTH-1 downto 0);`	`y : out std_logic_vector(G_WIDTH-1 downto 0);`
`sum : in std_logic_vector(G_WIDTH-1 downto 0);`	`sum : in std_logic_vector(G_WIDTH-1 downto 0);`
`carry_out : in std_logic`	`carry_out : in std_logic`
`);`	`);`
`end entity tc_example;`	`end entity tc_example2;`

`No newline at end of file`	`No newline at end of file`