URL https://opencores.org/ocsvn/pltbutils/pltbutils/trunk

Subversion Repositories pltbutils

[/] [pltbutils/] [branches/] [dev_beta0002/] [sim/] [modelsim_tb_pltbutils/] [bin/] [comp.do] - Diff between revs 2 and 27

Rev 2	Rev 27
Line 2...	Line 2...
`# ModelSim do-script for compiling design and testbench`	`# ModelSim do-script for compiling design and testbench`
`vlib work`	`vlib work`
`vcom -novopt -work work \`	`vcom -novopt -work work \`
`../../../src/vhdl/txt_util.vhd \`	`../../../src/vhdl/txt_util.vhd \`
`../../../src/vhdl/pltbutils_type_pkg.vhd \`	`../../../src/vhdl/pltbutils_type_pkg.vhd \`
	`../../../src/vhdl/pltbutils_user_cfg_pkg.vhd \`
`../../../src/vhdl/pltbutils_func_pkg.vhd \`	`../../../src/vhdl/pltbutils_func_pkg.vhd \`
`../../../src/vhdl/pltbutils_comp.vhd \`	`../../../src/vhdl/pltbutils_comp.vhd \`
`../../../src/vhdl/pltbutils_comp_pkg.vhd \`	`../../../src/vhdl/pltbutils_comp_pkg.vhd \`
`../../../bench/vhdl/tb_pltbutils.vhd`	`../../../bench/vhdl/tb_pltbutils.vhd`

`No newline at end of file`	`No newline at end of file`