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-- See pltbutils_comp.vhd for a description of the components.
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-- See pltbutils_comp.vhd for a description of the components.
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component pltbutils_clkgen is
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component pltbutils_clkgen is
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generic (
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generic (
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G_PERIOD : time := 10 ns
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G_PERIOD : time := 10 ns;
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G_INITVALUE : std_logic := '0'
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);
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);
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port (
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port (
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clk_o : out std_logic;
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clk_o : out std_logic;
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clk_n_o : out std_logic;
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stop_sim_i : in std_logic
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stop_sim_i : in std_logic
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);
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);
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end component pltbutils_clkgen;
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end component pltbutils_clkgen;
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-- Instansiation template
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-- Instansiation template
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-- (copy to your own file and remove the comment characters):
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-- (copy to your own file and remove the comment characters):
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--pltbutils_clkgen0 : pltbutils_clkgen
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--pltbutils_clkgen0 : pltbutils_clkgen
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-- generic map (
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-- generic map (
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-- G_PERIOD => G_PERIOD
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-- G_PERIOD => G_PERIOD,
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-- G_INITVALUE => '0'
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-- )
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-- )
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-- port map (
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-- port map (
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-- clk_o => clk,
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-- clk_o => clk,
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-- clk_n_o => clk_n,
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-- stop_sim_i => stop_sim
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-- stop_sim_i => stop_sim
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-- );
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-- );
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end package pltbutils_comp_pkg;
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end package pltbutils_comp_pkg;
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