| Line 24... |
Line 24... |
---- Author(s): ----
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---- Author(s): ----
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---- - Per Larsson, pela@opencores.org ----
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---- - Per Larsson, pela@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2013-2014 Authors and OPENCORES.ORG ----
|
---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
---- restriction provided that this copyright statement is not ----
|
---- restriction provided that this copyright statement is not ----
|
---- removed from the file and that any derivative work contains ----
|
---- removed from the file and that any derivative work contains ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- the original copyright notice and the associated disclaimer. ----
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| Line 65... |
Line 65... |
end entity tb_template;
|
end entity tb_template;
|
|
|
architecture bhv of tb_template is
|
architecture bhv of tb_template is
|
|
|
-- Simulation status- and control signals
|
-- Simulation status- and control signals
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signal test_num : integer;
|
-- for accessing .stop_sim and for viewing in waveform window
|
-- VHDL-1993:
|
signal pltbs : pltbs_t := C_PLTBS_INIT;
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--signal test_name : string(pltbutils_test_name'range);
|
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--signal info : string(pltbutils_info'range);
|
|
-- VHDL-2002:
|
|
signal test_name : string(pltbutils_sc.test_name'range);
|
|
signal info : string(pltbutils_sc.info'range);
|
|
|
|
signal checks : integer;
|
|
signal errors : integer;
|
|
signal stop_sim : std_logic;
|
|
|
|
-- DUT stimuli and response signals
|
-- DUT stimuli and response signals
|
signal clk : std_logic;
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signal clk : std_logic;
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signal rst : std_logic;
|
signal rst : std_logic;
|
-- < Template info: add more DUT stimuli and response signals here. >
|
-- < Template info: add more DUT stimuli and response signals here. >
|
|
|
begin
|
begin
|
|
|
-- Simulation status and control for viewing in waveform window
|
|
-- VHDL-1993:
|
|
--test_num <= pltbutils_test_num;
|
|
--test_name <= pltbutils_test_name;
|
|
--checks <= pltbutils_chk_cnt;
|
|
--errors <= pltbutils_err_cnt;
|
|
-- VHDL-2002:
|
|
test_num <= pltbutils_sc.test_num;
|
|
test_name <= pltbutils_sc.test_name;
|
|
info <= pltbutils_sc.info;
|
|
checks <= pltbutils_sc.chk_cnt;
|
|
errors <= pltbutils_sc.err_cnt;
|
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stop_sim <= pltbutils_sc.stop_sim;
|
|
|
|
|
|
dut0 : entity work.template
|
dut0 : entity work.template
|
generic map (
|
generic map (
|
-- < Template info: add DUT generics here, if any. >
|
-- < Template info: add DUT generics here, if any. >
|
)
|
)
|
port map (
|
port map (
|
| Line 115... |
Line 91... |
generic map(
|
generic map(
|
G_PERIOD => G_CLK_PERIOD
|
G_PERIOD => G_CLK_PERIOD
|
)
|
)
|
port map(
|
port map(
|
clk_o => clk,
|
clk_o => clk,
|
stop_sim_i => stop_sim
|
stop_sim_i => pltbs.stop_sim
|
);
|
);
|
|
|
tc0 : entity work.tc_example
|
tc0 : entity work.tc_example
|
generic map (
|
generic map (
|
-- < Template info: add generics for testcase component here, if any. >
|
-- < Template info: add generics for testcase component here, if any. >
|
