| Line 66... |
Line 66... |
rst <= '1';
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rst <= '1';
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carry_in <= '0';
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carry_in <= '0';
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x <= (others => '0');
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x <= (others => '0');
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y <= (others => '0');
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y <= (others => '0');
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testname(1, "Reset test", pltbutils_sc);
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starttest(1, "Reset test", pltbutils_sc);
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waitclks(2, clk, pltbutils_sc);
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waitclks(2, clk, pltbutils_sc);
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check("Sum during reset", sum, 0, pltbutils_sc);
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check("Sum during reset", sum, 0, pltbutils_sc);
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check("Carry out during reset", carry_out, '0', pltbutils_sc);
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check("Carry out during reset", carry_out, '0', pltbutils_sc);
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rst <= '0';
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rst <= '0';
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endtest(pltbutils_sc);
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testname(2, "Simple sum test", pltbutils_sc);
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starttest(2, "Simple sum test", pltbutils_sc);
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carry_in <= '0';
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carry_in <= '0';
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x <= std_logic_vector(to_unsigned(1, x'length));
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x <= std_logic_vector(to_unsigned(1, x'length));
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y <= std_logic_vector(to_unsigned(2, x'length));
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y <= std_logic_vector(to_unsigned(2, x'length));
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waitclks(2, clk, pltbutils_sc);
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waitclks(2, clk, pltbutils_sc);
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check("Sum", sum, 3, pltbutils_sc);
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check("Sum", sum, 3, pltbutils_sc);
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check("Carry out", carry_out, '0', pltbutils_sc);
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check("Carry out", carry_out, '0', pltbutils_sc);
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endtest(pltbutils_sc);
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testname(3, "Simple carry in test", pltbutils_sc);
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starttest(3, "Simple carry in test", pltbutils_sc);
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print(G_DISABLE_BUGS=0, pltbutils_sc, "Bug here somewhere");
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print(G_DISABLE_BUGS=0, pltbutils_sc, "Bug here somewhere");
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carry_in <= '1';
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carry_in <= '1';
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x <= std_logic_vector(to_unsigned(1, x'length));
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x <= std_logic_vector(to_unsigned(1, x'length));
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y <= std_logic_vector(to_unsigned(2, x'length));
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y <= std_logic_vector(to_unsigned(2, x'length));
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waitclks(2, clk, pltbutils_sc);
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waitclks(2, clk, pltbutils_sc);
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check("Sum", sum, 4, pltbutils_sc);
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check("Sum", sum, 4, pltbutils_sc);
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check("Carry out", carry_out, '0', pltbutils_sc);
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check("Carry out", carry_out, '0', pltbutils_sc);
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print(pltbutils_sc, "");
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print(pltbutils_sc, "");
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endtest(pltbutils_sc);
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testname(4, "Simple carry out test", pltbutils_sc);
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starttest(4, "Simple carry out test", pltbutils_sc);
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carry_in <= '0';
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carry_in <= '0';
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x <= std_logic_vector(to_unsigned(2**G_WIDTH-1, x'length));
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x <= std_logic_vector(to_unsigned(2**G_WIDTH-1, x'length));
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y <= std_logic_vector(to_unsigned(1, x'length));
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y <= std_logic_vector(to_unsigned(1, x'length));
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waitclks(2, clk, pltbutils_sc);
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waitclks(2, clk, pltbutils_sc);
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check("Sum", sum, 0, pltbutils_sc);
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check("Sum", sum, 0, pltbutils_sc);
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check("Carry out", carry_out, '1', pltbutils_sc);
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check("Carry out", carry_out, '1', pltbutils_sc);
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endtest(pltbutils_sc);
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endsim(pltbutils_sc, true);
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endsim(pltbutils_sc, true);
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wait;
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wait;
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end process p_tc1;
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end process p_tc1;
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end architecture tc1;
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end architecture tc1;
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No newline at end of file
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No newline at end of file
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