OpenCores
URL https://opencores.org/ocsvn/pltbutils/pltbutils/trunk

Subversion Repositories pltbutils

[/] [pltbutils/] [tags/] [v1.3/] [bench/] [vhdl/] [tb_pltbutils.vhd] - Diff between revs 2 and 25

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 2 Rev 25
Line 122... Line 122...
    end if;
    end if;
  end process p_clk_cnt;
  end process p_clk_cnt;
 
 
  -- Testcase
  -- Testcase
  p_tc1 : process
  p_tc1 : process
 
    variable v_expected_tests_cnt  : integer := 0;
    variable v_expected_checks_cnt : integer := 0;
    variable v_expected_checks_cnt : integer := 0;
    variable v_expected_errors_cnt : integer := 0;
    variable v_expected_errors_cnt : integer := 0;
  begin
  begin
 
 
    print("<Testing startsim()>");
    print("<Testing startsim()>");
Line 134... Line 135...
    assert test_num  = 0
    assert test_num  = 0
      report "test_num after startsim() incorrect"
      report "test_num after startsim() incorrect"
      severity error;
      severity error;
    print("<Done testing startsim()>");
    print("<Done testing startsim()>");
 
 
    print("<Testing testname() with auto-incrementing test_num>");
    print("<Testing starttest() with auto-incrementing test_num>");
    testname("TestName1", pltbutils_sc);
    starttest("TestName1", pltbutils_sc);
 
    v_expected_tests_cnt := v_expected_tests_cnt + 1;
    wait until rising_edge(clk);
    wait until rising_edge(clk);
    assert test_num  = 1
    assert test_num  = 1
      report "test_num after startsim() incorrect"
      report "test_num after starttest() incorrect"
      severity error;
      severity error;
    print("<Done testing testname() with auto-incrementing test_num()>");
    print("<Done testing starttest() with auto-incrementing test_num()>");
 
 
    print("<Testing testname() with explicit test_num>");
    print("<Testing endtest()>");
    testname(3, "TestName2", pltbutils_sc);
    endtest(pltbutils_sc);
 
    print("<Done testing endtest()>");
 
 
 
    print("<Testing starttest() with explicit test_num>");
 
    starttest(3, "TestName2", pltbutils_sc);
 
    v_expected_tests_cnt := v_expected_tests_cnt + 1;
    wait until rising_edge(clk);
    wait until rising_edge(clk);
    assert test_num  = 3
    assert test_num  = 3
      report "test_num after startsim() incorrect"
      report "test_num after startsim() incorrect"
      severity error;
      severity error;
    print("<Done testing testname() with explicit test_num>");
    print("<Done testing starttest() with explicit test_num>");
 
 
    print("<Testing waitclks()>");
    print("<Testing waitclks()>");
    clk_cnt_clr <= true;
    clk_cnt_clr <= true;
    wait until rising_edge(clk);
    wait until rising_edge(clk);
    clk_cnt_clr <= false;
    clk_cnt_clr <= false;
Line 418... Line 425...
    expected_checks_cnt   <= v_expected_checks_cnt;
    expected_checks_cnt   <= v_expected_checks_cnt;
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
    v_expected_errors_cnt := v_expected_errors_cnt + 1;
    expected_errors_cnt   <= v_expected_errors_cnt;
    expected_errors_cnt   <= v_expected_errors_cnt;
    print("<Done testing check() boolean expresson>");
    print("<Done testing check() boolean expresson>");
 
 
 
    print("<Testing endtest()>");
 
    endtest(pltbutils_sc);
 
    print("<Done testing endtest()>");
 
 
    wait until rising_edge(clk);
    wait until rising_edge(clk);
    print("<Testing endsim()>");
    print("<Testing endsim()>");
 
    print("Expected number of tests:  " & str(v_expected_tests_cnt));
    print("Expected number of checks: " & str(v_expected_checks_cnt));
    print("Expected number of checks: " & str(v_expected_checks_cnt));
    print("Expected number of errors: " & str(v_expected_errors_cnt));
    print("Expected number of errors: " & str(v_expected_errors_cnt));
    wait until rising_edge(clk);
    wait until rising_edge(clk);
    endsim(pltbutils_sc, true);
    endsim(pltbutils_sc, true);
    wait until rising_edge(clk);
    wait until rising_edge(clk);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.