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-- pltbutils_clkgen
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-- pltbutils_clkgen
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-- Creates a clock for use in a testbech.
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-- Creates a clock for use in a testbech.
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-- A non-inverted as well as an inverted output is available,
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-- use one or both depending on if you need a single-ended or
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-- differential clock.
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-- The clock stops when input port stop_sim goes '1'.
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-- The clock stops when input port stop_sim goes '1'.
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-- This makes the simulator stop (unless there are other infinite
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-- This makes the simulator stop (unless there are other infinite
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-- processes running in the simulation).
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-- processes running in the simulation).
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity pltbutils_clkgen is
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entity pltbutils_clkgen is
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generic (
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generic (
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G_PERIOD : time := 10 ns
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G_PERIOD : time := 10 ns;
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G_INITVALUE : std_logic := '0'
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);
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);
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port (
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port (
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clk_o : out std_logic;
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clk_o : out std_logic;
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clk_n_o : out std_logic;
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stop_sim_i : in std_logic
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stop_sim_i : in std_logic
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);
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);
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end entity pltbutils_clkgen;
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end entity pltbutils_clkgen;
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architecture bhv of pltbutils_clkgen is
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architecture bhv of pltbutils_clkgen is
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constant C_HALF_PERIOD : time := G_PERIOD / 2;
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constant C_HALF_PERIOD : time := G_PERIOD / 2;
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signal clk : std_logic := '0';
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signal clk : std_logic := G_INITVALUE;
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begin
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begin
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clk <= not clk and not stop_sim_i after C_HALF_PERIOD;
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clk <= not clk and not stop_sim_i after C_HALF_PERIOD;
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clk_o <= clk;
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clk_o <= clk;
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clk_n_o <= not clk;
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end architecture bhv;
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end architecture bhv;
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