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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Per Larsson, pela.opencores@gmail.com ----
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---- - Per Larsson, pela.opencores@gmail.com ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2013-2014 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.pltbutils_func_pkg.all;
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use work.pltbutils_func_pkg.all;
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entity tc_template2 is
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entity tc_template2 is
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generic (
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generic (
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-- < Template info: add generics here if needed, or remove the generic block >
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G_SKIPTESTS : std_logic_vector := (
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'0', -- Dummy
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'0', -- Test 1
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'0' -- Test 2
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-- ... etc
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)
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-- < Template info: add more generics here if needed >
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);
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);
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port (
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port (
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pltbs : out pltbs_t;
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pltbs : out pltbs_t;
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clk : in std_logic; -- Template example
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clk : in std_logic; -- Template example
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rst : out std_logic; -- Template example
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rst : out std_logic -- Template example
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-- < Template info: add more ports for testcase component here. >
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-- < Template info: add more ports for testcase component here. >
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-- < Inputs on the DUT should be outputs here, >
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-- < Inputs on the DUT should be outputs here, >
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-- < and vice versa. >
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-- < and vice versa. >
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-- < Exception: clocks are inputs both on DUT >
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-- < Exception: clocks are inputs both on DUT >
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-- < and here. >
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-- < and here. >
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