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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pp_types.all;
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use work.pp_types.all;
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use work.pp_utilities.all;
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use work.pp_utilities.all;
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--! @brief Simple cache module.
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--! @brief Simple read-only direct-mapped instruction cache.
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entity pp_cache is
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entity pp_icache is
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generic(
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generic(
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LINE_SIZE : natural := 8; --! Number of words per cache way
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LINE_SIZE : natural := 4; --! Number of words per cache line
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NUM_WAYS : natural := 2; --! Number of ways per set
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NUM_LINES : natural := 128 --! Number of lines in the cache
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NUM_SETS : natural := 128 --! Number of sets in the cache
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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Line 36... |
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-- Wishbone interface:
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-- Wishbone interface:
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wb_inputs : in wishbone_master_inputs;
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wb_inputs : in wishbone_master_inputs;
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wb_outputs : out wishbone_master_outputs
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wb_outputs : out wishbone_master_outputs
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);
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);
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end entity pp_cache;
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end entity pp_icache;
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architecture behaviour of pp_cache is
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architecture behaviour of pp_icache is
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-- Input-related signals:
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-- Counter types:
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signal input_address_set : std_logic_vector(log2(NUM_SETS) - 1 downto 0);
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subtype line_counter_type is natural range 0 to NUM_LINES;
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signal input_address_word : std_logic_vector(log2(LINE_SIZE / 4) - 1 downto 0);
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subtype word_counter_type is natural range 0 to LINE_SIZE;
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signal input_address_tag : std_logic_vector(31 - log2(NUM_SETS) - log2(LINE_SIZE / 4) downto 0);
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signal input_address_cached : boolean;
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-- Cache line types:
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subtype cache_line_type is std_logic_vector((LINE_SIZE * 32) - 1 downto 0);
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type cache_line_word_array is array(0 to LINE_SIZE - 1) of std_logic_vector(31 downto 0);
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type cache_line_array is array(0 to NUM_LINES - 1) of cache_line_type;
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-- Cache tag type:
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subtype cache_tag_type is std_logic_vector(31 - log2(LINE_SIZE * 4) - log2(NUM_LINES) downto 0);
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type cache_tag_array is array(0 to NUM_LINES - 1) of cache_tag_type;
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-- Cache memories:
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signal cache_memory : cache_line_array;
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signal tag_memory : cache_tag_array;
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signal valid : std_logic_vector(NUM_LINES - 1 downto 0) := (others => '0');
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attribute ram_style : string;
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attribute ram_style of cache_memory: signal is "block";
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--attribute ram_style of tag_memory: signal is "block";
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-- Cache controller signals:
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-- Cache controller signals:
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type state_type is (IDLE, SINGLE_READ, SINGLE_WRITE);
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type state_type is (IDLE, CACHE_READ_STALL, SINGLE_READ, SINGLE_WRITE,
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LOAD_CACHELINE_START, LOAD_CACHELINE_WAIT_ACK, LOAD_CACHELINE_FINISH);
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signal state : state_type := IDLE;
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signal state : state_type := IDLE;
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-- Is the current input address in the cache?
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signal input_address_cached : boolean;
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-- Input address components:
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signal input_address_line : std_logic_vector(log2(NUM_LINES) - 1 downto 0);
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signal input_address_word : std_logic_vector(log2(LINE_SIZE) - 1 downto 0);
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signal input_address_tag : std_logic_vector(31 - log2(LINE_SIZE * 4) - log2(NUM_LINES) downto 0);
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-- Cacheline matching the current input address:
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signal current_cache_line, cache_lookup : cache_line_type;
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signal current_cache_line_words : cache_line_word_array;
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signal current_tag : cache_tag_type;
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-- Base address to store a cacheline to:
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signal cl_store_address : std_logic_vector(31 downto log2(LINE_SIZE * 4));
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-- Base address to load a cacheline from:
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signal cl_load_address : std_logic_vector(31 downto log2(LINE_SIZE * 4));
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-- Cache line to load:
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signal cl_current_line : line_counter_type;
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-- Current word being loaded/stored:
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signal cl_current_word : word_counter_type;
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-- Buffer for holding a cache line while loading:
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signal load_buffer : cache_line_type;
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signal load_buffer_tag : cache_tag_type;
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-- Causes a cache line to be stored in the cache memory:
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signal store_cache_line : std_logic;
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-- Set when the current input address matches a cache line:
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signal cache_hit : std_logic;
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-- For regular reads:
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signal read_ack : std_logic;
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signal read_data_out : std_logic_vector(31 downto 0);
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-- For regular writes:
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signal write_ack : std_logic;
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-- Gets the amount to shift output data to the processor with for requests of size != 32 bits:
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-- Gets the amount to shift output data to the processor with for requests of size != 32 bits:
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function get_data_shift(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
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function get_data_shift(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
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return natural is
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return natural is
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begin
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begin
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case size is
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case size is
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| Line 80... |
Line 135... |
when others =>
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when others =>
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return 0;
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return 0;
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end case;
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end case;
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end function get_data_shift;
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end function get_data_shift;
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-- Gets the value of the sel signals to the wishbone interconnect for the specified
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-- operand size and address.
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function get_data_sel(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
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return std_logic_vector is
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begin
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begin
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case size is
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when b"01" =>
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--assert is_pow2(LINE_SIZE) report "Cache line size must be a power of 2!" severity FAILURE;
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case address(1 downto 0) is
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--assert is_pow2(NUM_LINES) report "Number of cache lines must be a power of 2!" severity FAILURE;
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when b"00" =>
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return b"0001";
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-- Check if the current input address should be/is in the cache:
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when b"01" =>
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input_address_cached <= cached_areas(to_integer(unsigned(mem_address_in(31 downto 27)))) = '1';
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return b"0010";
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when b"10" =>
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mem_data_out <= current_cache_line_words(to_integer(unsigned(input_address_word))) when
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return b"0100";
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input_address_cached and cache_enable = '1' and cache_flush = '0'
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when b"11" =>
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else read_data_out;
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return b"1000";
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mem_read_ack <= (cache_hit and mem_read_req)
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when others =>
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when state = IDLE and input_address_cached and cache_enable = '1' and cache_flush = '0'
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return b"0001";
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else read_ack;
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end case;
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write_ack <= wb_inputs.ack when state = SINGLE_WRITE else '0';
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when b"10" =>
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mem_write_ack <= write_ack;
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if address(1) = '0' then
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return b"0011";
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input_address_line <= mem_address_in(log2(LINE_SIZE * 4) + log2(NUM_LINES) - 1 downto log2(LINE_SIZE * 4));
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else
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input_address_tag <= mem_address_in(31 downto log2(LINE_SIZE * 4) + log2(NUM_LINES));
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return b"1100";
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find_word: process(clk)
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begin
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if rising_edge(clk) then
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input_address_word <= mem_address_in(log2(LINE_SIZE * 4) - 1 downto 2);
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end if;
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end if;
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when others =>
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end process find_word;
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return b"1111";
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end case;
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end function get_data_sel;
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cacheline_lookup: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if store_cache_line = '1' then
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cache_memory(cl_current_line) <= load_buffer;
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end if;
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-- Decompose the input address:
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current_cache_line <= cache_memory(to_integer(unsigned(input_address_line)));
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input_address_word <= mem_address_in(log2(LINE_SIZE / 4) - 1 downto 0);
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end if;
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input_address_set <= mem_address_in(log2(NUM_SETS) + log2(LINE_SIZE / 4) - 1 downto log2(LINE_SIZE / 4));
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end process cacheline_lookup;
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input_address_tag <= mem_address_in(31 downto log2(NUM_SETS) + log2(LINE_SIZE / 4));
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-- Check if the current input address should be/is in the cache:
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decompose_cache_line: for i in 0 to LINE_SIZE - 1 generate
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input_address_cached <= cached_areas(to_integer(unsigned(mem_address_in(31 downto 27)))) = '1';
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current_cache_line_words(i) <= current_cache_line(32 * i + 31 downto 32 * i);
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end generate decompose_cache_line;
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tag_lookup: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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cache_hit <= '0';
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else
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if store_cache_line = '1' then
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tag_memory(cl_current_line) <= load_buffer_tag;
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end if;
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-- Acknowledge signals:
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current_tag <= tag_memory(to_integer(unsigned(input_address_line)));
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mem_write_ack <= '1' when state = SINGLE_WRITE and wb_inputs.ack = '1' else '0';
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cache_hit <= valid(to_integer(unsigned(input_address_line))) and to_std_logic(tag_memory(to_integer(unsigned(input_address_line))) = input_address_tag);
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end if;
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end if;
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end process tag_lookup;
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controller: process(clk)
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controller: process(clk)
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variable current_word : std_logic_vector(31 downto 0);
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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state <= IDLE;
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state <= IDLE;
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wb_outputs.cyc <= '0';
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wb_outputs.cyc <= '0';
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wb_outputs.stb <= '0';
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wb_outputs.stb <= '0';
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mem_read_ack <= '0';
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store_cache_line <= '0';
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read_ack <= '0';
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valid <= (others => '0');
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read_data_out <= (others => '0');
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else
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else
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case state is
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case state is
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when IDLE =>
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when IDLE =>
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mem_read_ack <= '0';
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read_ack <= '0';
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if cache_flush = '1' then
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--if input_address_cached and cache_enable = '1' then
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valid <= (others => '0');
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-- if mem_read_req = '1' then
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elsif input_address_cached and cache_enable = '1' then
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-- elsif mem_write_req = '1' then
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if (mem_read_req = '1' or mem_write_req = '1') and cache_hit = '0' then
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-- end if;
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wb_outputs.adr <= mem_address_in(31 downto log2(LINE_SIZE * 4)) & (log2(LINE_SIZE * 4) - 1 downto 0 => '0');
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--else
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wb_outputs.cyc <= '1';
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if mem_read_req = '1' then -- Do an uncached read
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wb_outputs.we <= '0';
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wb_outputs.sel <= (others => '1');
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load_buffer_tag <= input_address_tag;
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cl_load_address <= mem_address_in(31 downto log2(LINE_SIZE * 4));
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cl_store_address <= input_address_tag & input_address_line;
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cl_current_line <= to_integer(unsigned(input_address_line));
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cl_current_word <= 0;
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state <= LOAD_CACHELINE_START;
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end if;
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else
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if mem_read_req = '1' and read_ack = '0' then -- Do an uncached read
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wb_outputs.adr <= mem_address_in;
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wb_outputs.adr <= mem_address_in;
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wb_outputs.sel <= get_data_sel(mem_data_size, mem_address_in);
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wb_outputs.sel <= wb_get_data_sel(mem_data_size, mem_address_in);
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wb_outputs.cyc <= '1';
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wb_outputs.cyc <= '1';
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wb_outputs.stb <= '1';
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wb_outputs.stb <= '1';
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wb_outputs.we <= '0';
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wb_outputs.we <= '0';
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state <= SINGLE_READ;
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state <= SINGLE_READ;
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elsif mem_write_req = '1' then -- Do an uncached write
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elsif mem_write_req = '1' then -- Do an uncached write
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wb_outputs.adr <= mem_address_in;
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wb_outputs.adr <= mem_address_in;
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wb_outputs.dat <= std_logic_vector(shift_left(unsigned(mem_data_in),
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wb_outputs.dat <= std_logic_vector(shift_left(unsigned(mem_data_in),
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get_data_shift(mem_data_size, mem_address_in)));
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get_data_shift(mem_data_size, mem_address_in)));
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wb_outputs.sel <= get_data_sel(mem_data_size, mem_address_in);
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wb_outputs.sel <= wb_get_data_sel(mem_data_size, mem_address_in);
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wb_outputs.cyc <= '1';
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wb_outputs.cyc <= '1';
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wb_outputs.stb <= '1';
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wb_outputs.stb <= '1';
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wb_outputs.we <= '1';
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wb_outputs.we <= '1';
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state <= SINGLE_WRITE;
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state <= SINGLE_WRITE;
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end if;
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end if;
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--end if;
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end if;
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when CACHE_READ_STALL =>
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state <= IDLE;
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when SINGLE_READ =>
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when SINGLE_READ =>
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if wb_inputs.ack = '1' then
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if wb_inputs.ack = '1' then
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mem_data_out <= std_logic_vector(shift_right(unsigned(wb_inputs.dat),
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read_data_out <= std_logic_vector(shift_right(unsigned(wb_inputs.dat),
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get_data_shift(mem_data_size, mem_address_in)));
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get_data_shift(mem_data_size, mem_address_in)));
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wb_outputs.cyc <= '0';
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wb_outputs.cyc <= '0';
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wb_outputs.stb <= '0';
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wb_outputs.stb <= '0';
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mem_read_ack <= '1';
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read_ack <= '1';
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state <= IDLE;
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state <= IDLE;
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end if;
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end if;
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when SINGLE_WRITE =>
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when SINGLE_WRITE =>
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if wb_inputs.ack = '1' then
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if wb_inputs.ack = '1' then
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wb_outputs.cyc <= '0';
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wb_outputs.cyc <= '0';
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wb_outputs.stb <= '0';
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wb_outputs.stb <= '0';
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wb_outputs.we <= '0';
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wb_outputs.we <= '0';
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state <= IDLE;
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state <= IDLE;
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end if;
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end if;
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when LOAD_CACHELINE_START =>
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wb_outputs.stb <= '1';
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wb_outputs.we <= '0';
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wb_outputs.adr <= cl_load_address & std_logic_vector(to_unsigned(cl_current_word, log2(LINE_SIZE))) & b"00";
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state <= LOAD_CACHELINE_WAIT_ACK;
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when LOAD_CACHELINE_WAIT_ACK =>
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if wb_inputs.ack = '1' then
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wb_outputs.stb <= '0';
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load_buffer(cl_current_word * 32 + 31 downto cl_current_word * 32) <= wb_inputs.dat;
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if natural(cl_current_word) = LINE_SIZE - 1 then
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wb_outputs.cyc <= '0';
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store_cache_line <= '1';
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state <= LOAD_CACHELINE_FINISH;
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else
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cl_current_word <= cl_current_word + 1;
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state <= LOAD_CACHELINE_START;
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end if;
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end if;
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when LOAD_CACHELINE_FINISH =>
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store_cache_line <= '0';
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valid(cl_current_line) <= '1';
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state <= CACHE_READ_STALL;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process controller;
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end process controller;
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