| Line 3... |
Line 3... |
// Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
|
// Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
|
|
|
#ifndef POTATO_H
|
#ifndef POTATO_H
|
#define POTATO_H
|
#define POTATO_H
|
|
|
|
// Number of IRQs supported:
|
|
#define POTATO_NUM_IRQS 8
|
|
|
|
// Implementation-specific CSRs:
|
|
#define CSR_PP_CACHECTRL 0x790
|
|
|
// Exception cause values:
|
// Exception cause values:
|
#define CAUSE_INSTR_MISALIGN 0x00
|
#define CAUSE_INSTR_MISALIGN 0x00
|
#define CAUSE_INSTR_FETCH 0x01
|
#define CAUSE_INSTR_FETCH 0x01
|
#define CAUSE_INVALID_INSTR 0x02
|
#define CAUSE_INVALID_INSTR 0x02
|
#define CAUSE_BREAKPOINT 0x03
|
#define CAUSE_BREAKPOINT 0x03
|
| Line 23... |
Line 29... |
|
|
// Status register bit indices:
|
// Status register bit indices:
|
#define STATUS_IE 0 // Enable Interrupts
|
#define STATUS_IE 0 // Enable Interrupts
|
#define STATUS_IE1 3 // Previous value of Enable Interrupts
|
#define STATUS_IE1 3 // Previous value of Enable Interrupts
|
|
|
|
// Cache control register bit indices:
|
|
#define CSR_PP_CACHECTRL_ICACHE_EN 0
|
|
|
#define potato_enable_interrupts() asm volatile("csrsi mstatus, 1 << %[ie_bit]\n" \
|
#define potato_enable_interrupts() asm volatile("csrsi mstatus, 1 << %[ie_bit]\n" \
|
:: [ie_bit] "i" (STATUS_IE))
|
:: [ie_bit] "i" (STATUS_IE))
|
#define potato_disable_interrupts() asm volatile("csrci mstatus, 1 << %[ie_bit] | 1 << %[ie1_bit]\n" \
|
#define potato_disable_interrupts() asm volatile("csrci mstatus, 1 << %[ie_bit] | 1 << %[ie1_bit]\n" \
|
:: [ie_bit] "i" (STATUS_IE), [ie1_bit] "i" (STATUS_IE1))
|
:: [ie_bit] "i" (STATUS_IE), [ie1_bit] "i" (STATUS_IE1))
|
|
|
