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// Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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// Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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#ifndef POTATO_H
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#ifndef POTATO_H
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#define POTATO_H
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#define POTATO_H
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// This file contains various defines neccessary for using the Potato processor
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// with current RISC-V compilers. It also makes sure that applications keep
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// working even though the supervisor extension specification should change.
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// Control and status registers:
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#define CSR_SUP0 0x500
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#define CSR_SUP1 0x501
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#define CSR_EPC 0x502
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#define CSR_BADVADDR 0x503
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#define CSR_EVEC 0x508
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#define CSR_CAUSE 0x509
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#define CSR_STATUS 0x50a
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#define CSR_HARTID 0x50b
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#define CSR_TOHOST 0x51e
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#define CSR_FROMHOST 0x51f
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#define CSR_CYCLE 0xc00
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#define CSR_CYCLEH 0xc80
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#define CSR_TIME 0xc01
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#define CSR_TIMEH 0xc81
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#define CSR_INSTRET 0xc02
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#define CSR_INSTRETH 0xc82
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// Exception cause values:
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// Exception cause values:
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#define CAUSE_INSTR_MISALIGN 0x00
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#define CAUSE_INSTR_MISALIGN 0x00
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#define CAUSE_INSTR_FETCH 0x01
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#define CAUSE_INSTR_FETCH 0x01
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#define CAUSE_INVALID_INSTR 0x02
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#define CAUSE_INVALID_INSTR 0x02
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#define CAUSE_SYSCALL 0x06
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#define CAUSE_BREAKPOINT 0x03
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#define CAUSE_BREAKPOINT 0x07
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#define CAUSE_LOAD_MISALIGN 0x04
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#define CAUSE_LOAD_MISALIGN 0x08
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#define CAUSE_LOAD_ERROR 0x05
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#define CAUSE_STORE_MISALIGN 0x09
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#define CAUSE_STORE_MISALIGN 0x06
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#define CAUSE_LOAD_ERROR 0x0a
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#define CAUSE_STORE_ERROR 0x07
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#define CAUSE_STORE_ERROR 0x0b
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#define CAUSE_ECALL 0x0b
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#define CAUSE_FROMHOST 0x1e
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#define CAUSE_IRQ_BASE 0x10
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#define CAUSE_IRQ_BASE 0x10
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// Interrupt bit in the cause register:
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#define CAUSE_INTERRUPT_BIT 31
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// Status register bit indices:
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// Status register bit indices:
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#define STATUS_EI 2 // Enable Interrupts
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#define STATUS_IE 0 // Enable Interrupts
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#define STATUS_PEI 3 // Previous value of Enable Interrupts
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#define STATUS_IE1 3 // Previous value of Enable Interrupts
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#define STATUS_IM_MASK 0x00ff0000 // Interrupt Mask
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#define STATUS_PIM_MASK 0xff000000 // Previous Interrupt Mask
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#define potato_enable_interrupts() asm volatile("csrsi mstatus, 1 << %[ie_bit]\n" \
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:: [ie_bit] "i" (STATUS_IE))
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#define potato_enable_interrupts() asm volatile("csrsi %[status], 1 << %[ei_bit]\n" \
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#define potato_disable_interrupts() asm volatile("csrci mstatus, 1 << %[ie_bit] | 1 << %[ie1_bit]\n" \
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:: [status] "i" (CSR_STATUS), [ei_bit] "i" (STATUS_EI))
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:: [ie_bit] "i" (STATUS_IE), [ie1_bit] "i" (STATUS_IE1))
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#define potato_disable_interrupts() asm volatile("csrci %[status], 1 << %[ei_bit] | 1 << %[pei_bit]\n" \
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:: [status] "i" (CSR_STATUS), [ei_bit] "i" (STATUS_EI), [pei_bit] "i" (STATUS_PEI))
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#define potato_write_host(data) \
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#define potato_write_host(data) \
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do { \
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do { \
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register uint32_t temp = data; \
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register uint32_t temp = data; \
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asm volatile("csrw %[tohost], %[temp]\n" \
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asm volatile("csrw mtohost, %[temp]\n" \
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:: [tohost] "i" (CSR_TOHOST), [temp] "r" (temp)); \
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:: [temp] "r" (temp)); \
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} while(0);
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} while(0);
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#define potato_enable_irq(n) \
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#define potato_enable_irq(n) \
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do { \
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do { \
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register uint32_t temp = 0; \
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register uint32_t temp = 0; \
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asm volatile( \
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asm volatile( \
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"li %[temp], 1 << %[shift]\n" \
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"li %[temp], 1 << %[shift]\n" \
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"csrs %[status], %[temp]\n" \
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"csrs mie, %[temp]\n" \
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:: [temp] "r" (temp), [shift] "i" (n + 16), [status] "i" (CSR_STATUS)); \
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:: [temp] "r" (temp), [shift] "i" (n + 24)); \
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} while(0)
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} while(0)
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#define potato_disable_irq(n) \
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#define potato_disable_irq(n) \
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do { \
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do { \
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register uint32_t temp = 0; \
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register uint32_t temp = 0; \
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asm volatile( \
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asm volatile( \
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"li %[temp], 1 << %[shift]\n" \
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"li %[temp], 1 << %[shift]\n" \
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"csrc %[status], %[temp]\n" \
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"csrc mie, %[temp]\n" \
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:: [temp] "r" (temp), [shift] "i" (n + 24), [status] "i" (CSR_STATUS)); \
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:: [temp] "r" (temp), [shift] "i" (n + 24);) \
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} while(0)
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} while(0)
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#define potato_get_badvaddr(n) \
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#define potato_get_badaddr(n) \
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do { \
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do { \
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register uint32_t __temp = 0; \
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register uint32_t __temp = 0; \
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asm volatile ( \
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asm volatile ( \
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"csrr %[temp], %[badvaddr]\n" \
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"csrr %[temp], mbadaddr\n" \
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: [temp] "=r" (__temp) : [badvaddr] "i" (CSR_BADVADDR)); \
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: [temp] "=r" (__temp)); \
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n = __temp; \
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n = __temp; \
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} while(0)
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} while(0)
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#endif
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#endif
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