OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] [potato/] [trunk/] [benchmarks/] [start.S] - Diff between revs 16 and 20

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 16 Rev 20
Line 4... Line 4...
 
 
// This file contains startup and initialization code for the Potato benchmark
// This file contains startup and initialization code for the Potato benchmark
// applications.
// applications.
 
 
#include "platform.h"
#include "platform.h"
 
#include "potato.h"
 
 
.section .init
.section .init
 
 
.global _start
.global _start
_start:
_start:
Line 59... Line 60...
 
 
.section .text
.section .text
 
 
.global exception_handler_wrapper
.global exception_handler_wrapper
exception_handler_wrapper:
exception_handler_wrapper:
        // Save all registers that aren't saved by the IRQ handler function:
        // Save all registers (even those that are saved by the IRQ handler
        addi sp, sp, -64
        // function, to aid in debugging):
        sw ra, 0(sp)
        addi sp, sp, -124
        sw t0, 4(sp)
        sw x1, 0(sp)
        sw t1, 8(sp)
        sw x2, 4(sp)
        sw t2, 12(sp)
        sw x3, 8(sp)
        sw t3, 16(sp)
        sw x4, 12(sp)
        sw t4, 20(sp)
        sw x5, 16(sp)
        sw t5, 24(sp)
        sw x6, 20(sp)
        sw t6, 28(sp)
        sw x7, 24(sp)
        sw a0, 32(sp)
        sw x8, 28(sp)
        sw a1, 36(sp)
        sw x9, 32(sp)
        sw a2, 40(sp)
        sw x10, 36(sp)
        sw a3, 44(sp)
        sw x11, 40(sp)
        sw a4, 48(sp)
        sw x12, 44(sp)
        sw a5, 52(sp)
        sw x13, 48(sp)
        sw a6, 56(sp)
        sw x14, 52(sp)
        sw a7, 60(sp)
        sw x15, 56(sp)
 
        sw x16, 60(sp)
 
        sw x17, 64(sp)
 
        sw x18, 68(sp)
 
        sw x19, 72(sp)
 
        sw x20, 76(sp)
 
        sw x21, 80(sp)
 
        sw x22, 84(sp)
 
        sw x23, 88(sp)
 
        sw x24, 92(sp)
 
        sw x25, 96(sp)
 
        sw x26, 100(sp)
 
        sw x27, 104(sp)
 
        sw x28, 108(sp)
 
        sw x29, 112(sp)
 
        sw x30, 116(sp)
 
        sw x31, 120(sp)
 
 
        csrr a0, cause
        csrr a0, cause
        csrr a1, epc
        csrr a1, epc
 
        mv a2, sp
        jal exception_handler
        jal exception_handler
 
 
        // Restore the current state:
.hidden exception_return
        lw ra, 0(sp)
exception_return:
        lw t0, 4(sp)
        // Restore all registers:
        lw t1, 8(sp)
        lw x1, 0(sp)
        lw t2, 12(sp)
        lw x2, 4(sp)
        lw t3, 16(sp)
        lw x3, 8(sp)
        lw t4, 20(sp)
        lw x4, 12(sp)
        lw t5, 24(sp)
        lw x5, 16(sp)
        lw t6, 28(sp)
        lw x6, 20(sp)
        lw a0, 32(sp)
        lw x7, 24(sp)
        lw a1, 36(sp)
        lw x8, 28(sp)
        lw a2, 40(sp)
        lw x9, 32(sp)
        lw a3, 44(sp)
        lw x10, 36(sp)
        lw a4, 48(sp)
        lw x11, 40(sp)
        lw a5, 52(sp)
        lw x12, 44(sp)
        lw a6, 56(sp)
        lw x13, 48(sp)
        lw a7, 60(sp)
        lw x14, 52(sp)
        addi sp, sp, 64
        lw x15, 56(sp)
 
        lw x16, 60(sp)
 
        lw x17, 64(sp)
 
        lw x18, 68(sp)
 
        lw x19, 72(sp)
 
        lw x20, 76(sp)
 
        lw x21, 80(sp)
 
        lw x22, 84(sp)
 
        lw x23, 88(sp)
 
        lw x24, 92(sp)
 
        lw x25, 96(sp)
 
        lw x26, 100(sp)
 
        lw x27, 104(sp)
 
        lw x28, 108(sp)
 
        lw x29, 112(sp)
 
        lw x30, 116(sp)
 
        lw x31, 120(sp)
 
        addi sp, sp, 124
 
 
        sret
        sret
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.