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https://opencores.org/ocsvn/potato/potato/trunk
[/] [potato/] [trunk/] [example/] [README] - Diff between revs 8 and 12
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processor. It has been tested using Vivado 2014.4.
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processor. It has been tested using Vivado 2014.4.
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## Quick Start
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## Quick Start
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In order to use the design, first import all source files from the folders
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In order to use the design, first import all source files from the folders
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`src/`, `soc/` and `example/` into your project.
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`src/`, `soc/` and `example/` into your project. Make sure the testbench files
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(the files starting with "tb_") is added as simulation-only files.
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### Clocking
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### Clocking
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Then add a clock generator using the Clocking Wizard. To seamlessly integrate
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Add a clock generator using the Clocking Wizard. To seamlessly integrate
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it into the design, name it "clock_generator". Choose the following options:
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it into the design, name it "clock_generator". Choose the following options:
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* Frequency Synthesis
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* Frequency Synthesis
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* Safe Clock Startup
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* Safe Clock Startup
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Add a block RAM to use as instruction ROM using the Block Memory Generator.
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Add a block RAM to use as instruction ROM using the Block Memory Generator.
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Choose "Single Port ROM" as memory type, name it "instruction_rom" and set
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Choose "Single Port ROM" as memory type, name it "instruction_rom" and set
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port A width to 32 bits and port A depth to 2048. Initialize it with your
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port A width to 32 bits and port A depth to 2048. Initialize it with your
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application binary and, optionally, fill the remaining memory locations with
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application binary and, optionally, fill the remaining memory locations with
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0x00000013.
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0x00000013 (no-operation opcode).
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### Test it!
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### Test it!
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Now you can test it and hopefully it works :-)
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Now you can test it and hopefully it works :-)
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