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[/] [potato/] [trunk/] [example/] [toplevel.vhd] - Diff between revs 12 and 21

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Rev 12	Rev 21
Line 106...	Line 106...
`MODULE_IMEM, MODULE_DMEM, -- Memory modules`	`MODULE_IMEM, MODULE_DMEM, -- Memory modules`
`MODULE_GPIO1, MODULE_GPIO2, -- GPIO modules`	`MODULE_GPIO1, MODULE_GPIO2, -- GPIO modules`
`MODULE_UART, -- UART module`	`MODULE_UART, -- UART module`
`MODULE_TIMER, -- Timer module`	`MODULE_TIMER, -- Timer module`
`MODULE_DUMMY, -- Dummy module, used for invalid addresses`	`MODULE_DUMMY, -- Dummy module, used for invalid addresses`
`MODULE_NONE -- Boring no-module mode, uses the dummy module`	`MODULE_NONE -- Boring no-module mode`
`);`	`);`
`signal active_module : module_name;`	`signal active_module : module_name;`

`begin`	`begin`

Line 207...	Line 207...
`);`	`);`

`uart1: entity work.pp_soc_uart`	`uart1: entity work.pp_soc_uart`
`generic map(`	`generic map(`
`FIFO_DEPTH => 64,`	`FIFO_DEPTH => 64,`
`SAMPLE_CLK_DIVISOR => 27`	`--SAMPLE_CLK_DIVISOR => 27 -- For 50 MHz`
	`SAMPLE_CLK_DIVISOR => 33 -- For 60 MHz`
`) port map(`	`) port map(`
`clk => system_clk,`	`clk => system_clk,`
`reset => reset,`	`reset => reset,`
`txd => uart_txd,`	`txd => uart_txd,`
`rxd => uart_rxd,`	`rxd => uart_rxd,`
Line 318...	Line 319...
`ad_state <= BUSY;`	`ad_state <= BUSY;`
`elsif p_adr_out(31 downto 11) = b"000000000000000001011" then -- 0x5800`	`elsif p_adr_out(31 downto 11) = b"000000000000000001011" then -- 0x5800`
`active_module <= MODULE_TIMER;`	`active_module <= MODULE_TIMER;`
`ad_state <= BUSY;`	`ad_state <= BUSY;`
`else`	`else`
`--active_module <= MODULE_NONE;`
`active_module <= MODULE_DUMMY;`	`active_module <= MODULE_DUMMY;`
`ad_state <= BUSY;`	`ad_state <= BUSY;`
`end if;`	`end if;`
`end if;`	`end if;`
`when BUSY =>`	`when BUSY =>`

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[/] [potato/] [trunk/] [example/] [toplevel.vhd] - Diff between revs 12 and 21