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https://opencores.org/ocsvn/potato/potato/trunk
[/] [potato/] [trunk/] [example/] [toplevel.vhd] - Diff between revs 21 and 45
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| Rev 21 |
Rev 45 |
| Line 207... |
Line 207... |
);
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);
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uart1: entity work.pp_soc_uart
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uart1: entity work.pp_soc_uart
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generic map(
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generic map(
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FIFO_DEPTH => 64,
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FIFO_DEPTH => 64,
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--SAMPLE_CLK_DIVISOR => 27 -- For 50 MHz
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SAMPLE_CLK_DIVISOR => 27 -- For 50 MHz
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SAMPLE_CLK_DIVISOR => 33 -- For 60 MHz
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--SAMPLE_CLK_DIVISOR => 33 -- For 60 MHz
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) port map(
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) port map(
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clk => system_clk,
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clk => system_clk,
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reset => reset,
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reset => reset,
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txd => uart_txd,
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txd => uart_txd,
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rxd => uart_rxd,
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rxd => uart_rxd,
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| Line 299... |
Line 299... |
ad_state <= IDLE;
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ad_state <= IDLE;
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active_module <= MODULE_NONE;
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active_module <= MODULE_NONE;
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else
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else
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case ad_state is
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case ad_state is
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when IDLE =>
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when IDLE =>
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if p_cyc_out = '1' and p_stb_out = '1' then
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if p_cyc_out = '1' then
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if p_adr_out(31 downto 13) = b"0000000000000000000" then
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if p_adr_out(31 downto 13) = b"0000000000000000000" then
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active_module <= MODULE_IMEM;
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active_module <= MODULE_IMEM;
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ad_state <= BUSY;
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ad_state <= BUSY;
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elsif p_adr_out(31 downto 13) = b"0000000000000000001" then -- 0x2000
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elsif p_adr_out(31 downto 13) = b"0000000000000000001" then -- 0x2000
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active_module <= MODULE_DMEM;
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active_module <= MODULE_DMEM;
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| Line 322... |
Line 322... |
ad_state <= BUSY;
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ad_state <= BUSY;
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else
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else
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active_module <= MODULE_DUMMY;
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active_module <= MODULE_DUMMY;
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ad_state <= BUSY;
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ad_state <= BUSY;
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end if;
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end if;
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else
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active_module <= MODULE_NONE;
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end if;
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end if;
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when BUSY =>
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when BUSY =>
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if p_cyc_out = '0' then
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if p_cyc_out = '0' then
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active_module <= MODULE_NONE;
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active_module <= MODULE_NONE;
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ad_state <= IDLE;
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ad_state <= IDLE;
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