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[/] [potato/] [trunk/] [example/] [toplevel.vhd] - Diff between revs 58 and 61

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Rev 58 Rev 61
Line 5... Line 5... 
library ieee;
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_1164.all;
 
 
 
 
 
entity toplevel is
 
entity toplevel is
 
        port(
 
        port(
 
                clk       : in std_logic; -- System clock, 100 MHz
 
                clk       : in std_logic; -- External clock input, 100 MHz
 
                reset_n   : in std_logic; -- CPU reset signal, active low
 
                reset_n   : in std_logic; -- CPU reset signal, active low
 
 
 
 
 
                -- External interrupt input:
 
                -- External interrupt input:
 
                external_interrupt : in std_logic;
 
                external_interrupt : in std_logic;
 
 
 
 
 
                -- GPIO pins, must be inout to use with the GPIO module:
 
                -- GPIO pins, must be inout to use with the GPIO module:
 
                switches : inout std_logic_vector(15 downto 0);
 
                switches : inout std_logic_vector(15 downto 0);
 
                leds     : inout std_logic_vector(15 downto 0);
 
                leds     : inout std_logic_vector(15 downto 0);
 
 
 
 
 
                -- UART1 (host) pins:
 
                -- UART pins:
 
                uart_txd : out std_logic;
 
                uart_txd : out std_logic;
 
                uart_rxd : in  std_logic
 
                uart_rxd : in  std_logic;
 
 
 
 
 
 
 
                -- 7-Segment display pins:
 
 
 
                seg7_anode   : out std_logic_vector(7 downto 0);
 
 
 
                seg7_cathode : out std_logic_vector(6 downto 0)
 
        );
 
        );
 
end entity toplevel;
 
end entity toplevel;
 
 
 
 
 
architecture behaviour of toplevel is
 
architecture behaviour of toplevel is
 
        signal system_clk : std_logic;
 
        signal system_clk : std_logic;
Line 89... Line 93... 
        signal timer_dat_out : std_logic_vector(31 downto 0);
 
        signal timer_dat_out : std_logic_vector(31 downto 0);
 
        signal timer_we_in   : std_logic;
 
        signal timer_we_in   : std_logic;
 
        signal timer_cyc_in, timer_stb_in : std_logic;
 
        signal timer_cyc_in, timer_stb_in : std_logic;
 
        signal timer_ack_out : std_logic;
 
        signal timer_ack_out : std_logic;
 
 
 
 
 
 
 
        -- 7-Segment module wishbone interface:
 
 
 
        signal seg7_adr_in  : std_logic_vector( 0 downto 0);
 
 
 
        signal seg7_dat_in  : std_logic_vector(31 downto 0);
 
 
 
        signal seg7_dat_out : std_logic_vector(31 downto 0);
 
 
 
        signal seg7_we_in   : std_logic;
 
 
 
        signal seg7_cyc_in, seg7_stb_in : std_logic;
 
 
 
        signal seg7_ack_out : std_logic;
 
 
 
 
 
        -- Dummy module interface:
 
        -- Dummy module interface:
 
        signal dummy_dat_in  : std_logic_vector(31 downto 0);
 
        signal dummy_dat_in  : std_logic_vector(31 downto 0);
 
        signal dummy_dat_out : std_logic_vector(31 downto 0);
 
        signal dummy_dat_out : std_logic_vector(31 downto 0);
 
        signal dummy_we_in   : std_logic;
 
        signal dummy_we_in   : std_logic;
 
        signal dummy_cyc_in, dummy_stb_in : std_logic;
 
        signal dummy_cyc_in, dummy_stb_in : std_logic;
Line 105... Line 117... 
        type module_name is (
 
        type module_name is (
 
                        MODULE_IMEM, MODULE_DMEM,       -- Memory modules
 
                        MODULE_IMEM, MODULE_DMEM,       -- Memory modules
 
                        MODULE_GPIO1, MODULE_GPIO2,     -- GPIO modules
 
                        MODULE_GPIO1, MODULE_GPIO2,     -- GPIO modules
 
                        MODULE_UART,    -- UART module
 
                        MODULE_UART,    -- UART module
 
                        MODULE_TIMER,   -- Timer module
 
                        MODULE_TIMER,   -- Timer module
 
 
 
                        MODULE_7SEG,    -- 7-Segment module
 
                        MODULE_DUMMY,   -- Dummy module, used for invalid addresses
 
                        MODULE_DUMMY,   -- Dummy module, used for invalid addresses
 
                        MODULE_NONE             -- Boring no-module mode
 
                        MODULE_NONE             -- Boring no-module mode
 
                );
 
                );
 
        signal active_module : module_name;
 
        signal active_module : module_name;
 
 
 
 
Line 240... Line 253... 
                        wb_stb_in => timer_stb_in,
 
                        wb_stb_in => timer_stb_in,
 
                        wb_we_in => timer_we_in,
 
                        wb_we_in => timer_we_in,
 
                        wb_ack_out => timer_ack_out
 
                        wb_ack_out => timer_ack_out
 
                );
 
                );
 
 
 
 
 
 
 
        seg7_1: entity work.pp_soc_7seg
 
 
 
                generic map(
 
 
 
                        SWITCH_COUNT => 50000 -- For 50 MHz
 
 
 
                ) port map(
 
 
 
                        clk => system_clk,
 
 
 
                        reset => reset,
 
 
 
                        seg7_anode => seg7_anode,
 
 
 
                        seg7_cathode => seg7_cathode,
 
 
 
                        wb_adr_in => seg7_adr_in,
 
 
 
                        wb_dat_in => seg7_dat_in,
 
 
 
                        wb_dat_out => seg7_dat_out,
 
 
 
                        wb_cyc_in => seg7_cyc_in,
 
 
 
                        wb_stb_in => seg7_stb_in,
 
 
 
                        wb_we_in => seg7_we_in,
 
 
 
                        wb_ack_out => seg7_ack_out
 
 
 
                );
 
 
 
 
 
        dummy: entity work.pp_soc_dummy
 
        dummy: entity work.pp_soc_dummy
 
                port map(
 
                port map(
 
                        clk => system_clk,
 
                        clk => system_clk,
 
                        reset => reset,
 
                        reset => reset,
 
                        wb_dat_in => dummy_dat_in,
 
                        wb_dat_in => dummy_dat_in,
Line 258... Line 288... 
        dmem_cyc_in <= p_cyc_out when active_module = MODULE_DMEM else '0';
 
        dmem_cyc_in <= p_cyc_out when active_module = MODULE_DMEM else '0';
 
        gpio1_cyc_in <= p_cyc_out when active_module = MODULE_GPIO1 else '0';
 
        gpio1_cyc_in <= p_cyc_out when active_module = MODULE_GPIO1 else '0';
 
        gpio2_cyc_in <= p_cyc_out when active_module = MODULE_GPIO2 else '0';
 
        gpio2_cyc_in <= p_cyc_out when active_module = MODULE_GPIO2 else '0';
 
        uart_cyc_in <= p_cyc_out when active_module = MODULE_UART else '0';
 
        uart_cyc_in <= p_cyc_out when active_module = MODULE_UART else '0';
 
        timer_cyc_in <= p_cyc_out when active_module = MODULE_TIMER else '0';
 
        timer_cyc_in <= p_cyc_out when active_module = MODULE_TIMER else '0';
 
 
 
        seg7_cyc_in <= p_cyc_out when active_module = MODULE_7SEG else '0';
 
        dummy_cyc_in <= p_cyc_out when active_module = MODULE_DUMMY else '0';
 
        dummy_cyc_in <= p_cyc_out when active_module = MODULE_DUMMY else '0';
 
 
 
 
 
        imem_stb_in <= p_stb_out when active_module = MODULE_IMEM else '0';
 
        imem_stb_in <= p_stb_out when active_module = MODULE_IMEM else '0';
 
        dmem_stb_in <= p_stb_out when active_module = MODULE_DMEM else '0';
 
        dmem_stb_in <= p_stb_out when active_module = MODULE_DMEM else '0';
 
        gpio1_stb_in <= p_stb_out when active_module = MODULE_GPIO1 else '0';
 
        gpio1_stb_in <= p_stb_out when active_module = MODULE_GPIO1 else '0';
 
        gpio2_stb_in <= p_stb_out when active_module = MODULE_GPIO2 else '0';
 
        gpio2_stb_in <= p_stb_out when active_module = MODULE_GPIO2 else '0';
 
        uart_stb_in <= p_stb_out when active_module = MODULE_UART else '0';
 
        uart_stb_in <= p_stb_out when active_module = MODULE_UART else '0';
 
        timer_stb_in <= p_stb_out when active_module = MODULE_TIMER else '0';
 
        timer_stb_in <= p_stb_out when active_module = MODULE_TIMER else '0';
 
 
 
        seg7_stb_in <= p_stb_out when active_module = MODULE_7SEG else '0';
 
        dummy_stb_in <= p_stb_out when active_module = MODULE_DUMMY else '0';
 
        dummy_stb_in <= p_stb_out when active_module = MODULE_DUMMY else '0';
 
 
 
 
 
        imem_adr_in <= p_adr_out(12 downto 0);
 
        imem_adr_in <= p_adr_out(12 downto 0);
 
        dmem_adr_in <= p_adr_out(12 downto 0);
 
        dmem_adr_in <= p_adr_out(12 downto 0);
 
        gpio1_adr_in <= p_adr_out(3 downto 2);
 
        gpio1_adr_in <= p_adr_out(3 downto 2);
 
        gpio2_adr_in <= p_adr_out(3 downto 2);
 
        gpio2_adr_in <= p_adr_out(3 downto 2);
 
        uart_adr_in <=  p_adr_out(3 downto 2);
 
        uart_adr_in <=  p_adr_out(3 downto 2);
 
        timer_adr_in <= p_adr_out(3 downto 2);
 
        timer_adr_in <= p_adr_out(3 downto 2);
 
 
 
        seg7_adr_in <=  p_adr_out(2 downto 2);
 
 
 
 
 
        dmem_dat_in <= p_dat_out;
 
        dmem_dat_in <= p_dat_out;
 
        gpio1_dat_in <= p_dat_out;
 
        gpio1_dat_in <= p_dat_out;
 
        gpio2_dat_in <= p_dat_out;
 
        gpio2_dat_in <= p_dat_out;
 
        uart_dat_in <= p_dat_out(7 downto 0);
 
        uart_dat_in <= p_dat_out(7 downto 0);
 
        timer_dat_in <= p_dat_out;
 
        timer_dat_in <= p_dat_out;
 
 
 
        seg7_dat_in <= p_dat_out;
 
        dummy_dat_in <= p_dat_out;
 
        dummy_dat_in <= p_dat_out;
 
 
 
 
 
        dmem_sel_in <= p_sel_out;
 
        dmem_sel_in <= p_sel_out;
 
 
 
 
 
        gpio1_we_in <= p_we_out;
 
        gpio1_we_in <= p_we_out;
 
        gpio2_we_in <= p_we_out;
 
        gpio2_we_in <= p_we_out;
 
        dmem_we_in <= p_we_out;
 
        dmem_we_in <= p_we_out;
 
        uart_we_in <= p_we_out;
 
        uart_we_in <= p_we_out;
 
        timer_we_in <= p_we_out;
 
        timer_we_in <= p_we_out;
 
 
 
        seg7_we_in <= p_we_out;
 
        dummy_we_in <= p_we_out;
 
        dummy_we_in <= p_we_out;
 
 
 
 
 
        address_decoder: process(system_clk)
 
        address_decoder: process(system_clk)
 
        begin
 
        begin
 
                if rising_edge(system_clk) then
 
                if rising_edge(system_clk) then
Line 319... Line 354... 
                                                                active_module <= MODULE_UART;
 
                                                                active_module <= MODULE_UART;
 
                                                                ad_state <= BUSY;
 
                                                                ad_state <= BUSY;
 
                                                        elsif p_adr_out(31 downto 11) = b"000000000000000001011" then -- 0x5800
 
                                                        elsif p_adr_out(31 downto 11) = b"000000000000000001011" then -- 0x5800
 
                                                                active_module <= MODULE_TIMER;
 
                                                                active_module <= MODULE_TIMER;
 
                                                                ad_state <= BUSY;
 
                                                                ad_state <= BUSY;
 
 
 
                                                        elsif p_adr_out(31 downto 11) = b"000000000000000001100" then -- 0x6000
 
 
 
                                                                active_module <= MODULE_7SEG;
 
 
 
                                                                ad_state <= BUSY;
 
                                                        else
 
                                                        else
 
                                                                active_module <= MODULE_DUMMY;
 
                                                                active_module <= MODULE_DUMMY;
 
                                                                ad_state <= BUSY;
 
                                                                ad_state <= BUSY;
 
                                                        end if;
 
                                                        end if;
 
                                                else
 
                                                else
Line 359... Line 397... 
                                p_ack_in <= uart_ack_out;
 
                                p_ack_in <= uart_ack_out;
 
                                p_dat_in <= (31 downto 8 => '0') & uart_dat_out;
 
                                p_dat_in <= (31 downto 8 => '0') & uart_dat_out;
 
                        when MODULE_TIMER =>
 
                        when MODULE_TIMER =>
 
                                p_ack_in <= timer_ack_out;
 
                                p_ack_in <= timer_ack_out;
 
                                p_dat_in <= timer_dat_out;
 
                                p_dat_in <= timer_dat_out;
 
 
 
                        when MODULE_7SEG =>
 
 
 
                                p_ack_in <= seg7_ack_out;
 
 
 
                                p_dat_in <= seg7_dat_out;
 
                        when MODULE_DUMMY =>
 
                        when MODULE_DUMMY =>
 
                                p_ack_in <= dummy_ack_out;
 
                                p_ack_in <= dummy_ack_out;
 
                                p_dat_in <= dummy_dat_out;
 
                                p_dat_in <= dummy_dat_out;
 
                        when MODULE_NONE =>
 
                        when MODULE_NONE =>
 
                                p_ack_in <= '0';
 
                                p_ack_in <= '0';

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