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#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
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#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
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#define _ENV_PHYSICAL_SINGLE_CORE_H
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#define _ENV_PHYSICAL_SINGLE_CORE_H
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#include "encoding.h"
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#include "encoding.h"
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//#include "../hwacha_xcpt.h"
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#include "hwacha_xcpt.h"
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Begin Macro
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// Begin Macro
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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RVTEST_VEC_ENABLE; \
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RVTEST_VEC_ENABLE; \
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.endm
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.endm
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#define RVTEST_RV32U \
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#define RVTEST_RV32U \
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.macro init; \
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.macro init; \
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RVTEST_32_ENABLE; \
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.endm
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.endm
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#define RVTEST_RV32UF \
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#define RVTEST_RV32UF \
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.macro init; \
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.macro init; \
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RVTEST_32_ENABLE; \
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RVTEST_FP_ENABLE; \
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RVTEST_FP_ENABLE; \
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.endm
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.endm
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#define RVTEST_RV32UV \
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#define RVTEST_RV32UV \
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.macro init; \
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.macro init; \
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RVTEST_32_ENABLE; \
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RVTEST_FP_ENABLE; \
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RVTEST_FP_ENABLE; \
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RVTEST_VEC_ENABLE; \
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RVTEST_VEC_ENABLE; \
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.endm
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.endm
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#define RVTEST_RV64M \
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.macro init; \
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RVTEST_ENABLE_MACHINE; \
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.endm
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#define RVTEST_RV64S \
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#define RVTEST_RV64S \
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.macro init; \
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.macro init; \
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RVTEST_ENABLE_SUPERVISOR; \
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.endm
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#define RVTEST_RV64SV \
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.macro init; \
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RVTEST_ENABLE_SUPERVISOR; \
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RVTEST_VEC_ENABLE; \
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.endm
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#define RVTEST_RV32M \
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.macro init; \
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RVTEST_ENABLE_MACHINE; \
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.endm
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.endm
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#define RVTEST_RV32S \
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#define RVTEST_RV32S \
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.macro init; \
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.macro init; \
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RVTEST_32_ENABLE; \
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RVTEST_ENABLE_SUPERVISOR; \
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.endm
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.endm
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#define RVTEST_32_ENABLE \
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#ifdef __riscv64
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li a0, SR_S64; \
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# define CHECK_XLEN csrr a0, mcpuid; bltz a0, 1f; RVTEST_PASS; 1:
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csrc status, a0; \
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#else
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# define CHECK_XLEN csrr a0, mcpuid; bgez a0, 1f; RVTEST_PASS; 1:
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#endif
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#define RVTEST_ENABLE_SUPERVISOR \
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li a0, MSTATUS_PRV1 & (MSTATUS_PRV1 >> 1); \
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csrs mstatus, a0; \
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#define RVTEST_ENABLE_MACHINE \
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li a0, MSTATUS_PRV1; \
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csrs mstatus, a0; \
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#define RVTEST_FP_ENABLE \
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#define RVTEST_FP_ENABLE \
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li a0, SR_EF; \
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li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \
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csrs status, a0; \
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csrs mstatus, a0; \
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csrr a1, status; \
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csrr a0, mcpuid; \
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and a0, a0, a1; \
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andi a0, a0, 1 << ('D' - 'A'); /* test for D extension */ \
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bnez a0, 2f; \
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bnez a0, 1f; \
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RVTEST_PASS; \
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RVTEST_PASS; /* "pass" the test if FPU not present */ \
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2:fssr x0; \
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1:csrwi fcsr, 0
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#define RVTEST_VEC_ENABLE \
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#define RVTEST_VEC_ENABLE \
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li a0, SR_EA; \
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li a0, SSTATUS_XS & (SSTATUS_XS >> 1); \
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csrs status, a0; \
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csrs sstatus, a0; \
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csrr a1, status; \
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csrr a1, sstatus; \
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and a0, a0, a1; \
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and a0, a0, a1; \
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bnez a0, 2f; \
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bnez a0, 2f; \
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RVTEST_PASS; \
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RVTEST_PASS; \
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2: \
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2: \
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#define RISCV_MULTICORE_DISABLE \
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#define RISCV_MULTICORE_DISABLE \
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csrr a0, hartid; \
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csrr a0, mhartid; \
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1: bnez a0, 1b; \
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1: bnez a0, 1b
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#define EXTRA_TVEC_USER
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#define EXTRA_TVEC_SUPERVISOR
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#define EXTRA_TVEC_HYPERVISOR
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#define EXTRA_TVEC_MACHINE
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#define EXTRA_INIT
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#define EXTRA_INIT
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#define EXTRA_INIT_TIMER
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#define EXTRA_INIT_TIMER
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#define RVTEST_CODE_BEGIN \
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#define RVTEST_CODE_BEGIN \
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.text; \
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.text; \
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.align 4; \
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.align 6; \
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.global _start; \
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.weak stvec_handler; \
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.weak mtvec_handler; \
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tvec_user: \
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EXTRA_TVEC_USER; \
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/* test whether the test came from pass/fail */ \
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la t5, ecall; \
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csrr t6, mepc; \
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beq t5, t6, write_tohost; \
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/* test whether the stvec_handler target exists */ \
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la t5, stvec_handler; \
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bnez t5, mrts_routine; \
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/* test whether the mtvec_handler target exists */ \
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la t5, mtvec_handler; \
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bnez t5, mtvec_handler; \
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/* some other exception occurred */ \
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j other_exception; \
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.align 6; \
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tvec_supervisor: \
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EXTRA_TVEC_SUPERVISOR; \
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csrr t5, mcause; \
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bgez t5, tvec_user; \
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mrts_routine: \
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mrts; \
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.align 6; \
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tvec_hypervisor: \
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EXTRA_TVEC_HYPERVISOR; \
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/* renting some space out here */ \
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other_exception: \
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1: ori TESTNUM, TESTNUM, 1337; /* some other exception occurred */ \
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write_tohost: \
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csrw mtohost, TESTNUM; \
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j write_tohost; \
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.align 6; \
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tvec_machine: \
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EXTRA_TVEC_MACHINE; \
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la t5, ecall; \
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csrr t6, mepc; \
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beq t5, t6, write_tohost; \
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la t5, mtvec_handler; \
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bnez t5, mtvec_handler; \
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j other_exception; \
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.align 6; \
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.globl _start; \
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_start: \
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_start: \
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RISCV_MULTICORE_DISABLE; \
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RISCV_MULTICORE_DISABLE; \
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CHECK_XLEN; \
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la t0, stvec_handler; \
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csrw stvec, t0; \
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li t0, MSTATUS_PRV1 | MSTATUS_PRV2 | MSTATUS_IE1 | MSTATUS_IE2; \
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csrc mstatus, t0; \
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init; \
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init; \
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EXTRA_INIT; \
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EXTRA_INIT; \
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EXTRA_INIT_TIMER; \
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EXTRA_INIT_TIMER; \
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la t0, 1f; \
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csrw mepc, t0; \
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csrr a0, mhartid; \
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eret; \
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1:
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// End Macro
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// End Macro
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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#define RVTEST_CODE_END \
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#define RVTEST_CODE_END \
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ecall: ecall; \
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j ecall
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Pass/Fail Macro
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// Pass/Fail Macro
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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#define RVTEST_PASS \
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#define RVTEST_PASS \
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fence; \
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fence; \
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csrw tohost, 1; \
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li TESTNUM, 1; \
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1: j 1b; \
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j ecall
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#define TESTNUM x28
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#define TESTNUM x28
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#define RVTEST_FAIL \
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#define RVTEST_FAIL \
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fence; \
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fence; \
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beqz TESTNUM, 1f; \
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1: beqz TESTNUM, 1b; \
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sll TESTNUM, TESTNUM, 1; \
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sll TESTNUM, TESTNUM, 1; \
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or TESTNUM, TESTNUM, 1; \
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or TESTNUM, TESTNUM, 1; \
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csrw tohost, TESTNUM; \
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j ecall
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1: j 1b; \
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Data Section Macro
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// Data Section Macro
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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