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[/] [potato/] [trunk/] [riscv-tests/] [test_macros.h] - Diff between revs 6 and 58

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Rev 6 Rev 58
Line 490... Line 490...
 
 
#define TEST_FCVT_D_S( testnum, result, val1 ) \
#define TEST_FCVT_D_S( testnum, result, val1 ) \
  TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
  TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
                    fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
                    fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
 
 
#define TEST_FP_OP1_S( testnum, inst, result, val1 ) \
#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
  TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
                    inst f3, f0; fmv.x.s a0, f3)
                    inst f3, f0; fmv.x.s a0, f3)
 
 
#define TEST_FP_OP1_D( testnum, inst, result, val1 ) \
#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
  TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
                    inst f3, f0; fmv.x.d a0, f3)
                    inst f3, f0; fmv.x.d a0, f3)
 
 
#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
                    inst f3, f0, f1; fmv.x.s a0, f3)
                    inst f3, f0, f1; fmv.x.s a0, f3)
Line 568... Line 568...
#-----------------------------------------------------------------------
#-----------------------------------------------------------------------
# RV64SV MACROS
# RV64SV MACROS
#-----------------------------------------------------------------------
#-----------------------------------------------------------------------
 
 
#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
  csrs status, SR_EI; \
 
  la a0, handler ## testnum; \
  la a0, handler ## testnum; \
  csrw evec, a0; \
  csrw stvec, a0; \
  vsetcfg nxreg, nfreg; \
  vsetcfg nxreg, nfreg; \
  li a0, 4; \
  li a0, 4; \
  vsetvl a0, a0; \
  vsetvl a0, a0; \
  la a0, src1; \
  la a0, src1; \
  la a1, src2; \
  la a1, src2; \
Line 595... Line 594...
  add x2, x2, x3; \
  add x2, x2, x3; \
  stop; \
  stop; \
handler ## testnum: \
handler ## testnum: \
  vxcptkill; \
  vxcptkill; \
  li TESTNUM,2; \
  li TESTNUM,2; \
  vxcptcause a0; \
  csrr a0, scause; \
  li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
  li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
  bne a0,a1,fail; \
  bne a0,a1,fail; \
  vxcptaux a0; \
  csrr a0, sbadaddr; \
  la a1, illegal ## testnum; \
  la a1, illegal ## testnum; \
  lw a2, 0(a1); \
  lw a2, 0(a1); \
  bne a0, a2, fail; \
  bne a0, a2, fail; \
  vsetcfg 32,0; \
  vsetcfg 32,0; \
  li a0,4; \
  li a0,4; \
Line 629... Line 628...
  ld a1,24(a3); \
  ld a1,24(a3); \
  li TESTNUM,5; \
  li TESTNUM,5; \
  bne a1,a2,fail; \
  bne a1,a2,fail; \
 
 
#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
  csrs status, SR_EI; \
 
  la a0, handler ## testnum; \
  la a0, handler ## testnum; \
  csrw evec, a0; \
  csrw stvec, a0; \
  vsetcfg nxreg, nfreg; \
  vsetcfg nxreg, nfreg; \
  li a0, 4; \
  li a0, 4; \
  vsetvl a0, a0; \
  vsetvl a0, a0; \
  la a0, src1; \
  la a0, src1; \
  la a1, src2; \
  la a1, src2; \
Line 655... Line 653...
  add x2, x2, x3; \
  add x2, x2, x3; \
  stop; \
  stop; \
handler ## testnum: \
handler ## testnum: \
  vxcptkill; \
  vxcptkill; \
  li TESTNUM,2; \
  li TESTNUM,2; \
  vxcptcause a0; \
  csrr a0, scause; \
  li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
  li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
  bne a0,a1,fail; \
  bne a0,a1,fail; \
  vxcptaux a0; \
  csrr a0, sbadaddr; \
  la a1,illegal ## testnum; \
  la a1,illegal ## testnum; \
  bne a0,a1,fail; \
  bne a0,a1,fail; \
  vsetcfg 32,0; \
  vsetcfg 32,0; \
  li a0,4; \
  li a0,4; \
  vsetvl a0,a0; \
  vsetvl a0,a0; \
Line 694... Line 692...
#-----------------------------------------------------------------------
#-----------------------------------------------------------------------
 
 
#define TEST_PASSFAIL \
#define TEST_PASSFAIL \
        bne x0, TESTNUM, pass; \
        bne x0, TESTNUM, pass; \
fail: \
fail: \
        RVTEST_FAIL \
        RVTEST_FAIL; \
pass: \
pass: \
        RVTEST_PASS \
        RVTEST_PASS \
 
 
 
 
#-----------------------------------------------------------------------
#-----------------------------------------------------------------------

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