| Line 23... |
Line 23... |
rd_write : out std_logic;
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rd_write : out std_logic;
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branch : out branch_type;
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branch : out branch_type;
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|
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-- Exception signals:
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-- Exception signals:
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decode_exception : out std_logic;
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decode_exception : out std_logic;
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decode_exception_cause : out std_logic_vector(4 downto 0);
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decode_exception_cause : out csr_exception_cause;
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|
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-- Control register signals:
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-- Control register signals:
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csr_write : out csr_write_mode;
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csr_write : out csr_write_mode;
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csr_imm : out std_logic; --! Indicating an immediate variant of the csrr* instructions.
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csr_imm : out std_logic; --! Indicating an immediate variant of the csrr* instructions.
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|
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| Line 43... |
Line 43... |
);
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);
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end entity pp_control_unit;
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end entity pp_control_unit;
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|
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architecture behaviour of pp_control_unit is
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architecture behaviour of pp_control_unit is
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signal exception : std_logic;
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signal exception : std_logic;
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signal exception_cause : std_logic_vector(4 downto 0);
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signal exception_cause : csr_exception_cause;
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signal alu_op_temp : alu_operation;
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signal alu_op_temp : alu_operation;
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begin
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begin
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|
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csr_imm <= funct3(2);
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csr_imm <= funct3(2);
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alu_op <= alu_op_temp;
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alu_op <= alu_op_temp;
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| Line 123... |
Line 123... |
if funct3 = b"000" then
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if funct3 = b"000" then
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rd_write <= '0';
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rd_write <= '0';
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|
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if funct12 = x"000" then
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if funct12 = x"000" then
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exception <= '1';
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exception <= '1';
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exception_cause <= CSR_CAUSE_SYSCALL;
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exception_cause <= CSR_CAUSE_ECALL;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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elsif funct12 = x"001" then
|
elsif funct12 = x"001" then
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exception <= '1';
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exception <= '1';
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exception_cause <= CSR_CAUSE_BREAKPOINT;
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exception_cause <= CSR_CAUSE_BREAKPOINT;
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branch <= BRANCH_NONE;
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branch <= BRANCH_NONE;
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elsif funct12 = x"800" then
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elsif funct12 = CSR_EPC_ERET then
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exception <= '0';
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exception <= '0';
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exception_cause <= CSR_CAUSE_NONE;
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exception_cause <= CSR_CAUSE_NONE;
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branch <= BRANCH_SRET;
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branch <= BRANCH_SRET;
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else
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else
|
exception <= '1';
|
exception <= '1';
|
