| Line 17... |
Line 17... |
--! instructions for manipulation of control and status registers from the
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--! instructions for manipulation of control and status registers from the
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--! currently unpublished supervisor extension.
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--! currently unpublished supervisor extension.
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entity pp_core is
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entity pp_core is
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generic(
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generic(
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PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID.
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PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID.
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RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000" --! Address of the first instruction to execute.
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RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000200" --! Address of the first instruction to execute.
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);
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);
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port(
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port(
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-- Control inputs:
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-- Control inputs:
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clk : in std_logic; --! Processor clock
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clk : in std_logic; --! Processor clock
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reset : in std_logic; --! Reset signal
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reset : in std_logic; --! Reset signal
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| Line 73... |
Line 73... |
signal csr_read_data : std_logic_vector(31 downto 0);
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signal csr_read_data : std_logic_vector(31 downto 0);
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signal csr_read_writeable : boolean;
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signal csr_read_writeable : boolean;
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signal csr_read_address, csr_read_address_p : csr_address;
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signal csr_read_address, csr_read_address_p : csr_address;
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|
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-- Status register outputs:
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-- Status register outputs:
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signal status : csr_status_register;
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signal mtvec : std_logic_vector(31 downto 0);
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signal evec : std_logic_vector(31 downto 0);
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signal mie : std_logic_vector(31 downto 0);
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signal ie, ie1 : std_logic;
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-- Internal interrupt signals:
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signal software_interrupt, timer_interrupt : std_logic;
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-- Load hazard detected in the execute stage:
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-- Load hazard detected in the execute stage:
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signal load_hazard_detected : std_logic;
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signal load_hazard_detected : std_logic;
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|
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-- Branch targets:
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-- Branch targets:
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| Line 180... |
Line 184... |
PROCESSOR_ID => PROCESSOR_ID
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PROCESSOR_ID => PROCESSOR_ID
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) port map(
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) port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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timer_clk => timer_clk,
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timer_clk => timer_clk,
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irq => irq,
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count_instruction => wb_count_instruction,
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count_instruction => wb_count_instruction,
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fromhost_data => fromhost_data,
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fromhost_data => fromhost_data,
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fromhost_updated => fromhost_write_en,
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fromhost_updated => fromhost_write_en,
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tohost_data => tohost_data,
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tohost_data => tohost_data,
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tohost_updated => tohost_write_en,
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tohost_updated => tohost_write_en,
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| Line 193... |
Line 198... |
write_address => wb_csr_address,
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write_address => wb_csr_address,
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write_data_in => wb_csr_data,
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write_data_in => wb_csr_data,
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write_mode => wb_csr_write,
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write_mode => wb_csr_write,
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exception_context => wb_exception_context,
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exception_context => wb_exception_context,
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exception_context_write => wb_exception,
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exception_context_write => wb_exception,
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status_out => status,
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mie_out => mie,
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evec_out => evec
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mtvec_out => mtvec,
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ie_out => ie,
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ie1_out => ie1,
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software_interrupt_out => software_interrupt,
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timer_interrupt_out => timer_interrupt
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);
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);
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|
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csr_read_address <= id_csr_address when stall_ex = '0' else csr_read_address_p;
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csr_read_address <= id_csr_address when stall_ex = '0' else csr_read_address_p;
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|
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store_previous_csr_addr: process(clk, stall_ex)
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store_previous_csr_addr: process(clk, stall_ex)
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begin
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begin
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if rising_edge(clk) and stall_ex = '0' then
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if rising_edge(clk) and stall_ex = '0' then
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csr_read_address_p <= id_csr_address;
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csr_read_address_p <= id_csr_address;
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end if;
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end if;
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| Line 297... |
Line 305... |
clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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stall => stall_ex,
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stall => stall_ex,
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flush => flush_ex,
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flush => flush_ex,
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irq => irq,
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irq => irq,
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software_interrupt => software_interrupt,
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timer_interrupt => timer_interrupt,
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dmem_address => ex_dmem_address,
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dmem_address => ex_dmem_address,
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dmem_data_size => ex_dmem_data_size,
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dmem_data_size => ex_dmem_data_size,
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dmem_data_out => ex_dmem_data_out,
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dmem_data_out => ex_dmem_data_out,
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dmem_read_req => ex_dmem_read_req,
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dmem_read_req => ex_dmem_read_req,
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dmem_write_req => ex_dmem_write_req,
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dmem_write_req => ex_dmem_write_req,
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| Line 335... |
Line 345... |
mem_op_out => ex_mem_op,
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mem_op_out => ex_mem_op,
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mem_size_in => id_mem_size,
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mem_size_in => id_mem_size,
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mem_size_out => ex_mem_size,
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mem_size_out => ex_mem_size,
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count_instruction_in => id_count_instruction,
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count_instruction_in => id_count_instruction,
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count_instruction_out => ex_count_instruction,
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count_instruction_out => ex_count_instruction,
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status_in => status,
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ie_in => ie,
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evec_in => evec,
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ie1_in => ie1,
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evec_out => exception_target,
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mie_in => mie,
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mtvec_in => mtvec,
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mtvec_out => exception_target,
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decode_exception_in => id_exception,
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decode_exception_in => id_exception,
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decode_exception_cause_in => id_exception_cause,
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decode_exception_cause_in => id_exception_cause,
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exception_out => exception_taken,
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exception_out => exception_taken,
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exception_context_out => ex_exception_context,
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exception_context_out => ex_exception_context,
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jump_out => branch_taken,
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jump_out => branch_taken,
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