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--! Type used for specifying control and status register addresses.
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--! Type used for specifying control and status register addresses.
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subtype csr_address is std_logic_vector(11 downto 0);
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subtype csr_address is std_logic_vector(11 downto 0);
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--! Type used for exception cause values.
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--! Type used for exception cause values.
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subtype csr_exception_cause is std_logic_vector(4 downto 0);
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subtype csr_exception_cause is std_logic_vector(5 downto 0); -- Upper bit is the interrupt bit
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--! Converts an exception cause to a std_logic_vector.
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function to_std_logic_vector(input : in csr_exception_cause) return std_logic_vector;
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function to_std_logic_vector(input : in csr_exception_cause) return std_logic_vector;
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--! Control/status register write mode:
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--! Control/status register write mode:
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type csr_write_mode is (
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type csr_write_mode is (
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CSR_WRITE_NONE, CSR_WRITE_SET, CSR_WRITE_CLEAR, CSR_WRITE_REPLACE
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CSR_WRITE_NONE, CSR_WRITE_SET, CSR_WRITE_CLEAR, CSR_WRITE_REPLACE
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);
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);
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-- Exception cause values:
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-- Exception cause values:
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constant CSR_CAUSE_INSTR_MISALIGN : csr_exception_cause := b"00000";
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constant CSR_CAUSE_INSTR_MISALIGN : csr_exception_cause := b"000000";
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constant CSR_CAUSE_INSTR_FETCH : csr_exception_cause := b"00001";
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constant CSR_CAUSE_INSTR_FETCH : csr_exception_cause := b"000001";
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constant CSR_CAUSE_INVALID_INSTR : csr_exception_cause := b"00010";
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constant CSR_CAUSE_INVALID_INSTR : csr_exception_cause := b"000010";
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constant CSR_CAUSE_SYSCALL : csr_exception_cause := b"00110";
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constant CSR_CAUSE_BREAKPOINT : csr_exception_cause := b"000011";
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constant CSR_CAUSE_BREAKPOINT : csr_exception_cause := b"00111";
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constant CSR_CAUSE_LOAD_MISALIGN : csr_exception_cause := b"000100";
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constant CSR_CAUSE_LOAD_MISALIGN : csr_exception_cause := b"01000";
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constant CSR_CAUSE_LOAD_ERROR : csr_exception_cause := b"000101";
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constant CSR_CAUSE_STORE_MISALIGN : csr_exception_cause := b"01001";
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constant CSR_CAUSE_STORE_MISALIGN : csr_exception_cause := b"000110";
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constant CSR_CAUSE_LOAD_ERROR : csr_exception_cause := b"01010";
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constant CSR_CAUSE_STORE_ERROR : csr_exception_cause := b"000111";
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constant CSR_CAUSE_STORE_ERROR : csr_exception_cause := b"01011";
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constant CSR_CAUSE_ECALL : csr_exception_cause := b"001011";
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constant CSR_CAUSE_FROMHOST : csr_exception_cause := b"11110";
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constant CSR_CAUSE_NONE : csr_exception_cause := b"011111";
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constant CSR_CAUSE_NONE : csr_exception_cause := b"11111";
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constant CSR_CAUSE_SOFTWARE_INT : csr_exception_cause := b"100000";
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constant CSR_CAUSE_IRQ_BASE : csr_exception_cause := b"10000";
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constant CSR_CAUSE_TIMER_INT : csr_exception_cause := b"100001";
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constant CSR_CAUSE_IRQ_BASE : csr_exception_cause := b"110000";
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-- Control register IDs, specified in the immediate of csr* instructions:
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constant CSR_STATUS : csr_address := x"50a";
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-- Control register IDs, specified in the immediate field of csr* instructions:
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constant CSR_HARTID : csr_address := x"50b";
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constant CSR_SUP0 : csr_address := x"500";
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constant CSR_SUP1 : csr_address := x"501";
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constant CSR_BADVADDR : csr_address := x"503";
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constant CSR_TOHOST : csr_address := x"51e";
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constant CSR_FROMHOST : csr_address := x"51f";
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constant CSR_CYCLE : csr_address := x"c00";
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constant CSR_CYCLE : csr_address := x"c00";
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constant CSR_CYCLEH : csr_address := x"c80";
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constant CSR_CYCLEH : csr_address := x"c80";
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constant CSR_TIME : csr_address := x"c01";
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constant CSR_TIME : csr_address := x"c01";
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constant CSR_TIMEH : csr_address := x"c81";
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constant CSR_TIMEH : csr_address := x"c81";
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constant CSR_INSTRET : csr_address := x"c02";
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constant CSR_INSTRET : csr_address := x"c02";
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constant CSR_INSTRETH : csr_address := x"c82";
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constant CSR_INSTRETH : csr_address := x"c82";
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constant CSR_EPC : csr_address := x"502";
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constant CSR_EVEC : csr_address := x"508";
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constant CSR_CAUSE : csr_address := x"509";
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-- Values used as control register IDs in SRET, SCALL and SBREAK:
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constant CSR_MCPUID : csr_address := x"f00";
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constant CSR_EPC_SRET : csr_address := x"800";
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constant CSR_MIMPID : csr_address := x"f01";
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constant CSR_MHARTID : csr_address := x"f10";
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constant CSR_MSTATUS : csr_address := x"300";
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constant CSR_MTVEC : csr_address := x"301";
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constant CSR_MTDELEG : csr_address := x"302";
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constant CSR_MIE : csr_address := x"304";
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constant CSR_MTIMECMP : csr_address := x"321";
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constant CSR_MTIME : csr_address := x"701";
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constant CSR_MSCRATCH : csr_address := x"340";
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constant CSR_MEPC : csr_address := x"341";
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constant CSR_MCAUSE : csr_address := x"342";
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constant CSR_MBADADDR : csr_address := x"343";
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constant CSR_MIP : csr_address := x"344";
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constant CSR_MTOHOST : csr_address := x"780";
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constant CSR_MFROMHOST : csr_address := x"781";
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-- Values used as control register IDs in ERET:
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constant CSR_EPC_ERET : csr_address := x"100";
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-- Offset into the exception vector for handling machine-mode exceptions:
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constant CSR_MTVEC_M_OFFSET : natural := 192;
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-- Additional CSRs from supervisor mode that aliases machine mode registers
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-- in this implementation:
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--constant CSR_STVEC : csr_address := x"101";
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--constant CSR_SEPC : csr_address := x"141";
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-- Status register bit indices:
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-- Status register bit indices:
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constant CSR_SR_S : natural := 0;
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constant CSR_SR_IE : natural := 0;
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constant CSR_SR_PS : natural := 1;
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constant CSR_SR_IE1 : natural := 3;
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constant CSR_SR_EI : natural := 2;
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constant CSR_SR_PEI : natural := 3;
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-- Status register in Potato:
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-- * Bit 0, S: Supervisor mode, always 1
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-- * Bit 1, PS: Previous supervisor mode bit, always 1
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-- * Bit 2, EI: Enable interrupts bit
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-- * Bit 3, PEI: Previous enable interrupts bit
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-- * Bits 23 downto 16, IM: Interrupt mask
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-- * Bits 31 downto 24, PIM: Previous interrupt mask
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-- Status register record:
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-- MIE and MIP register bit indices:
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type csr_status_register is
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constant CSR_MIE_MSIE : natural := 3;
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record
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constant CSR_MIE_MTIE : natural := 7;
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ei, pei : std_logic;
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constant CSR_MIP_MSIP : natural := CSR_MIE_MSIE;
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im, pim : std_logic_vector(7 downto 0);
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constant CSR_MIP_MTIP : natural := CSR_MIE_MTIE;
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end record;
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-- Exception context; this record contains all state that is stored
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-- Exception context; this record contains all state that can be manipulated
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-- when an exception is taken.
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-- when an exception is taken.
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type csr_exception_context is
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type csr_exception_context is
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record
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record
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status : csr_status_register;
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ie, ie1 : std_logic; -- Enable Interrupt bits
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cause : csr_exception_cause;
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cause : csr_exception_cause;
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badvaddr : std_logic_vector(31 downto 0);
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badaddr : std_logic_vector(31 downto 0);
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end record;
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end record;
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-- Reset value of the status register:
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--! Creates the value of the mstatus registe from the EI and EI1 bits.
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constant CSR_SR_DEFAULT : csr_status_register := (ei => '0', pei => '0', im => x"00", pim => x"00");
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function csr_make_mstatus(ie, ie1 : in std_logic) return std_logic_vector;
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-- Converts a status register record into an std_logic_vector:
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function to_std_logic_vector(input : in csr_status_register)
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return std_logic_vector;
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-- Converts an std_logic_vector into a status register record:
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function to_csr_status_register(input : in std_logic_vector(31 downto 0))
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return csr_status_register;
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--! Checks if a control register is writeable.
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function csr_is_writeable(csr : in csr_address) return boolean;
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end package pp_csr;
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end package pp_csr;
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package body pp_csr is
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package body pp_csr is
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function to_std_logic_vector(input : in csr_exception_cause)
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function to_std_logic_vector(input : in csr_exception_cause)
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return std_logic_vector is
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return std_logic_vector is
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begin
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begin
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return (31 downto 5 => '0') & input;
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return (31 => input(5), 30 downto 5 => '0') & input(4 downto 0);
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end function to_std_logic_vector;
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end function to_std_logic_vector;
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function to_std_logic_vector(input : in csr_status_register)
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function csr_make_mstatus(ie, ie1 : in std_logic) return std_logic_vector is
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return std_logic_vector is
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variable retval : std_logic_vector(31 downto 0);
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begin
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begin
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return input.pim & input.im & (15 downto 4 => '0') & input.pei & input.ei & '1' & '1';
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retval := (
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end function to_std_logic_vector;
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11 downto 10 => '1', -- PRV3
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8 downto 7 => '1', -- PRV2
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function to_csr_status_register(input : in std_logic_vector(31 downto 0))
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5 downto 4 => '1', -- PRV1
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return csr_status_register
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CSR_SR_IE1 => ie1, -- IE1
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is
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2 downto 1 => '1', -- PRV
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variable retval : csr_status_register;
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CSR_SR_IE => ie, -- IE
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begin
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others => '0');
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retval.ei := input(CSR_SR_EI);
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retval.pei := input(CSR_SR_PEI);
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retval.im := input(23 downto 16);
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retval.pim := input(31 downto 24);
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return retval;
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return retval;
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end function to_csr_status_register;
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end function csr_make_mstatus;
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function csr_is_writeable(csr : in csr_address) return boolean is
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begin
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case csr is
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when CSR_FROMHOST | CSR_CYCLE | CSR_CYCLEH | CSR_HARTID
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| CSR_TIME | CSR_TIMEH | CSR_INSTRET | CSR_INSTRETH
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| CSR_CAUSE | CSR_BADVADDR =>
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return false;
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when others =>
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return true;
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end case;
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end function csr_is_writeable;
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end package body pp_csr;
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end package body pp_csr;
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