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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pp_csr.all;
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use work.pp_csr.all;
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use work.pp_utilities.all;
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entity pp_csr_unit is
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entity pp_csr_unit is
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generic(
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generic(
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PROCESSOR_ID : std_logic_vector(31 downto 0)
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PROCESSOR_ID : std_logic_vector(31 downto 0)
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);
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);
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port(
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port(
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clk, timer_clk : in std_logic;
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clk, timer_clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- IRQ signals:
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irq : in std_logic_vector(7 downto 0);
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-- Count retired instruction:
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-- Count retired instruction:
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count_instruction : in std_logic;
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count_instruction : in std_logic;
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-- HTIF interface:
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-- HTIF interface:
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fromhost_data : in std_logic_vector(31 downto 0);
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fromhost_data : in std_logic_vector(31 downto 0);
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-- Exception context write port:
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-- Exception context write port:
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exception_context : in csr_exception_context;
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exception_context : in csr_exception_context;
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exception_context_write : in std_logic;
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exception_context_write : in std_logic;
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-- Interrupts originating from this unit:
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software_interrupt_out : out std_logic;
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timer_interrupt_out : out std_logic;
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-- Registers needed for exception handling, always read:
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-- Registers needed for exception handling, always read:
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status_out : out csr_status_register;
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mie_out : out std_logic_vector(31 downto 0);
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evec_out : out std_logic_vector(31 downto 0)
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mtvec_out : out std_logic_vector(31 downto 0);
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ie_out, ie1_out : out std_logic
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);
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);
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end entity pp_csr_unit;
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end entity pp_csr_unit;
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architecture behaviour of pp_csr_unit is
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architecture behaviour of pp_csr_unit is
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-- Implemented counters:
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-- Counters:
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signal counter_time : std_logic_vector(63 downto 0);
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signal counter_time : std_logic_vector(63 downto 0);
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signal counter_cycle : std_logic_vector(63 downto 0);
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signal counter_cycle : std_logic_vector(63 downto 0);
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signal counter_instret : std_logic_vector(63 downto 0);
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signal counter_instret : std_logic_vector(63 downto 0);
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-- Implemented registers:
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-- Machine time counter:
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signal sup0, sup1 : std_logic_vector(31 downto 0) := (others => '0');
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signal counter_mtime : std_logic_vector(31 downto 0);
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signal epc, evec : std_logic_vector(31 downto 0) := (others => '0');
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signal mtime_compare : std_logic_vector(31 downto 0);
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signal badvaddr : std_logic_vector(31 downto 0) := (others => '0');
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signal cause : csr_exception_cause;
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-- Machine-mode registers:
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signal mcause : csr_exception_cause;
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signal mbadaddr : std_logic_vector(31 downto 0);
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signal mscratch : std_logic_vector(31 downto 0);
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signal mepc : std_logic_vector(31 downto 0);
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signal mtvec : std_logic_vector(31 downto 0) := x"00000100";
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signal mie : std_logic_vector(31 downto 0) := (others => '0');
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-- Interrupt enable bits:
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signal ie, ie1 : std_logic;
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-- HTIF FROMHOST register:
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-- HTIF FROMHOST register:
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signal fromhost: std_logic_vector(31 downto 0);
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signal fromhost: std_logic_vector(31 downto 0);
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-- Status register:
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-- Interrupt signals:
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signal status_register : csr_status_register;
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signal timer_interrupt : std_logic;
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signal software_interrupt : std_logic;
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begin
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begin
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read_writeable <= csr_is_writeable(read_address);
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-- Interrupt signals:
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software_interrupt_out <= software_interrupt;
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timer_interrupt_out <= timer_interrupt;
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ie_out <= ie;
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ie1_out <= ie1;
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mie_out <= mie;
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-- The two upper bits of the CSR address encodes the accessibility of the CSR:
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read_writeable <= read_address(11 downto 10) /= b"11";
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--! Updates the FROMHOST register when new data is available.
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--! Updates the FROMHOST register when new data is available.
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htif_fromhost: process(clk)
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htif_fromhost: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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tohost_data <= (others => '0');
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tohost_data <= (others => '0');
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tohost_updated <= '0';
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tohost_updated <= '0';
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else
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else
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if write_mode /= CSR_WRITE_NONE and write_address = CSR_TOHOST then
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if write_mode /= CSR_WRITE_NONE and write_address = CSR_MTOHOST then
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tohost_data <= write_data_in;
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tohost_data <= write_data_in;
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tohost_updated <= '1';
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tohost_updated <= '1';
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else
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else
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tohost_updated <= '0';
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tohost_updated <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process htif_tohost;
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end process htif_tohost;
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mtime_counter: process(timer_clk, reset)
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begin
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if reset = '1' then -- Asynchronous reset because timer_clk is slower than clk
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counter_mtime <= (others => '0');
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elsif rising_edge(timer_clk) then
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counter_mtime <= std_logic_vector(unsigned(counter_mtime) + 1);
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end if;
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end process mtime_counter;
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mtime_interrupt: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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timer_interrupt <= '0';
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else
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if write_mode /= CSR_WRITE_NONE and write_address = CSR_MTIMECMP then
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timer_interrupt <= '0';
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elsif counter_mtime = mtime_compare then
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timer_interrupt <= '1';
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end if;
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end if;
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end if;
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end process mtime_interrupt;
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write: process(clk)
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write: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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status_register <= CSR_SR_DEFAULT;
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software_interrupt <= '0';
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mtvec <= x"00000100";
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mepc <= x"00000100";
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mie <= (others => '0');
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ie <= '0';
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ie1 <= '0';
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else
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else
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if exception_context_write = '1' then
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if exception_context_write = '1' then
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status_register <= exception_context.status;
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ie <= exception_context.ie;
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cause <= exception_context.cause;
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ie1 <= exception_context.ie1;
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badvaddr <= exception_context.badvaddr;
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mcause <= exception_context.cause;
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mbadaddr <= exception_context.badaddr;
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end if;
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end if;
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if write_mode /= CSR_WRITE_NONE then
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if write_mode /= CSR_WRITE_NONE then
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case write_address is
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case write_address is
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when CSR_STATUS =>
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when CSR_MSTATUS => -- Status register
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if exception_context_write = '0' then
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ie1 <= write_data_in(CSR_SR_IE1);
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status_register <= to_csr_status_register(write_data_in);
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ie <= write_data_in(CSR_SR_IE);
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end if;
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when CSR_MSCRATCH => -- Scratch register
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when CSR_EPC =>
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mscratch <= write_data_in;
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epc <= write_data_in;
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when CSR_MEPC => -- Exception return address
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when CSR_EVEC =>
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mepc <= write_data_in;
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evec <= write_data_in;
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--when CSR_MCAUSE => -- Exception cause
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when CSR_SUP0 =>
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-- mcause <= write_data_in(31) & write_data_in(4 downto 0);
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sup0 <= write_data_in;
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when CSR_MTVEC => -- Exception vector address
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when CSR_SUP1 =>
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mtvec <= write_data_in;
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sup1 <= write_data_in;
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when CSR_MTIMECMP => -- Time compare register
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mtime_compare <= write_data_in;
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when CSR_MIE => -- Interrupt enable register:
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mie <= write_data_in;
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when CSR_MIP => -- Interrupt pending register:
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software_interrupt <= write_data_in(CSR_MIP_MSIP);
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when others =>
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when others =>
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-- Ignore writes to invalid or read-only registers
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-- Ignore writes to invalid or read-only registers
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process write;
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end process write;
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status_out <= exception_context.status when exception_context_write = '1' else status_register;
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read: process(clk)
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read: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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--if exception_context_write = '1' then
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-- status_out <= exception_context.status;
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--else
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-- status_out <= status_register;
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--end if;
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if write_mode /= CSR_WRITE_NONE and write_address = CSR_EVEC then
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if write_mode /= CSR_WRITE_NONE and write_address = CSR_MTVEC then
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evec_out <= write_data_in;
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mtvec_out <= write_data_in;
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else
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else
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evec_out <= evec;
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mtvec_out <= mtvec;
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end if;
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end if;
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if write_mode /= CSR_WRITE_NONE and write_address = read_address then
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if write_mode /= CSR_WRITE_NONE and write_address = read_address then
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read_data_out <= write_data_in;
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read_data_out <= write_data_in;
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else
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else
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case read_address is
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case read_address is
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-- Status and control registers:
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-- Machine mode registers:
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when CSR_STATUS => -- Status register
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when CSR_MCPUID => -- CPU features register
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read_data_out <= to_std_logic_vector(status_register);
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read_data_out <= (
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when CSR_HARTID => -- Processor ID
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8 => '1', -- Set the bit corresponding to I
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others => '0');
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when CSR_MIMPID => -- Implementation/Implementor ID
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read_data_out <= (31 downto 16 => '0') & x"8000";
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-- The anonymous source ID, 0x8000 is used until an open-source implementation ID
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-- is available for use.
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when CSR_MHARTID => -- Hardware thread ID
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read_data_out <= PROCESSOR_ID;
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read_data_out <= PROCESSOR_ID;
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when CSR_FROMHOST => -- Fromhost data
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when CSR_MFROMHOST => -- Data from a host environment
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read_data_out <= fromhost;
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read_data_out <= fromhost;
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when CSR_EPC | CSR_EPC_SRET => -- Exception PC value
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when CSR_MSTATUS => -- Status register
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read_data_out <= epc;
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read_data_out <= csr_make_mstatus(ie, ie1);
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when CSR_EVEC => -- Exception handler address
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when CSR_MSCRATCH => -- Scratch register
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read_data_out <= evec;
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read_data_out <= mscratch;
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when CSR_CAUSE => -- Exception cause
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when CSR_MEPC => -- Exception PC value
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read_data_out <= to_std_logic_vector(cause);
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read_data_out <= mepc;
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when CSR_BADVADDR => -- Load/store address responsible for the exception
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when CSR_MTVEC => -- Exception vector address
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read_data_out <= badvaddr;
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read_data_out <= mtvec;
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when CSR_MTDELEG => -- Exception vector delegation register, unsupported
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-- Supporting registers:
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read_data_out <= (others => '0');
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when CSR_SUP0 =>
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when CSR_MIP => -- Interrupt pending
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read_data_out <= sup0;
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read_data_out <= irq & (CSR_MIP_MTIP => timer_interrupt, CSR_MIP_MSIP => software_interrupt,
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when CSR_SUP1 =>
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23 downto 8 => '0', 6 downto 4 => '0', 2 downto 0 => '0');
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read_data_out <= sup1;
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when CSR_MIE => -- Interrupt enable register
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read_data_out <= mie;
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when CSR_MBADADDR => -- Bad memory address
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read_data_out <= mbadaddr;
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when CSR_MCAUSE => -- Exception cause
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read_data_out <= mcause(5) & (30 downto 5 => '0') & mcause(4 downto 0); --to_std_logic_vector(mcause);
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-- Timers and counters:
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-- Timers and counters:
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when CSR_MTIME => -- Machine time counter register
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read_data_out <= counter_mtime;
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when CSR_MTIMECMP => -- Machine time compare register
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read_data_out <= mtime_compare;
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when CSR_TIME =>
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when CSR_TIME =>
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read_data_out <= counter_time(31 downto 0);
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read_data_out <= counter_time(31 downto 0);
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when CSR_TIMEH =>
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when CSR_TIMEH =>
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read_data_out <= counter_time(63 downto 32);
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read_data_out <= counter_time(63 downto 32);
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when CSR_CYCLE =>
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when CSR_CYCLE =>
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