| Line 38... |
Line 38... |
instruction_ready : out std_logic
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instruction_ready : out std_logic
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);
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);
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end entity pp_fetch;
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end entity pp_fetch;
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|
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architecture behaviour of pp_fetch is
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architecture behaviour of pp_fetch is
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--signal pc, pc_next : std_logic_vector(31 downto 0);
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--signal acknowledge, ready : std_logic;
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|
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signal pc : std_logic_vector(31 downto 0);
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signal pc : std_logic_vector(31 downto 0);
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signal pc_next : std_logic_vector(31 downto 0);
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signal pc_next : std_logic_vector(31 downto 0);
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signal cancel_fetch : std_logic;
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signal cancel_fetch : std_logic;
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begin
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begin
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|
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imem_address <= pc_next;
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imem_address <= pc_next when cancel_fetch = '0' else pc;
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|
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instruction_data <= imem_data_in;
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instruction_data <= imem_data_in;
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instruction_ready <= imem_ack and (not stall) and (not cancel_fetch);
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instruction_ready <= imem_ack and (not stall) and (not cancel_fetch);
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instruction_address <= pc;
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instruction_address <= pc;
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|
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--imem_req <= '1' when cancel_fetch = '0' and
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|
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imem_req <= '1';
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imem_req <= '1';
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|
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set_pc: process(clk)
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set_pc: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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| Line 79... |
Line 73... |
end if;
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end if;
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end process set_pc;
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end process set_pc;
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calc_next_pc: process(reset, stall, branch, exception, imem_ack, branch_target, evec, pc, cancel_fetch)
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calc_next_pc: process(reset, stall, branch, exception, imem_ack, branch_target, evec, pc, cancel_fetch)
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begin
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begin
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if reset = '1' then
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if exception = '1' then
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pc_next <= RESET_ADDRESS;
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elsif exception = '1' then
|
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pc_next <= evec;
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pc_next <= evec;
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elsif branch = '1' then
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elsif branch = '1' then
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pc_next <= branch_target;
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pc_next <= branch_target;
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elsif imem_ack = '1' and stall = '0' and cancel_fetch = '0' then
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elsif imem_ack = '1' and stall = '0' and cancel_fetch = '0' then
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pc_next <= std_logic_vector(unsigned(pc) + 4);
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pc_next <= std_logic_vector(unsigned(pc) + 4);
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