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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.pp_types.all;
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--! @brief The Potato Processor.
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--! @brief The Potato Processor.
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--! This file provides a Wishbone-compatible interface to the Potato processor.
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--! This file provides a Wishbone-compatible interface to the Potato processor.
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entity pp_potato is
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entity pp_potato is
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generic(
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generic(
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PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID.
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PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID.
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signal dmem_read_req : std_logic;
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signal dmem_read_req : std_logic;
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signal dmem_read_ack : std_logic;
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signal dmem_read_ack : std_logic;
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signal dmem_write_req : std_logic;
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signal dmem_write_req : std_logic;
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signal dmem_write_ack : std_logic;
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signal dmem_write_ack : std_logic;
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-- Wishbone signals:
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signal icache_inputs, dmem_if_inputs : wishbone_master_inputs;
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signal icache_outputs, dmem_if_outputs : wishbone_master_outputs;
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begin
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begin
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processor: entity work.pp_core
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processor: entity work.pp_core
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generic map(
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generic map(
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PROCESSOR_ID => PROCESSOR_ID,
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PROCESSOR_ID => PROCESSOR_ID,
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RESET_ADDRESS => RESET_ADDRESS
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RESET_ADDRESS => RESET_ADDRESS
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tohost_data => tohost_data,
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tohost_data => tohost_data,
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tohost_write_en => tohost_updated,
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tohost_write_en => tohost_updated,
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irq => irq
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irq => irq
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);
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);
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wb_if: entity work.pp_wb_adapter
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icache: entity work.pp_icache
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generic map(
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LINE_SIZE => 4,
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NUM_LINES => 128
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) port map(
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clk => clk,
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reset => reset,
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cache_enable => '1',
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cache_flush => '0',
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cached_areas => (others => '1'),
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mem_address_in => imem_address,
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mem_data_out => imem_data,
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mem_data_in => (others => '0'),
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mem_data_size => b"00",
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mem_read_req => imem_req,
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mem_read_ack => imem_ack,
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mem_write_req => '0',
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mem_write_ack => open,
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wb_inputs => icache_inputs,
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wb_outputs => icache_outputs
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);
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dmem_if: entity work.pp_wb_adapter
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port map(
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port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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imem_address => imem_address,
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imem_data_out => imem_data,
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imem_read_req => imem_req,
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imem_read_ack => imem_ack,
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dmem_address => dmem_address,
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dmem_address => dmem_address,
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dmem_data_in => dmem_data_out,
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dmem_data_in => dmem_data_out,
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dmem_data_out => dmem_data_in,
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dmem_data_out => dmem_data_in,
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dmem_data_size => dmem_data_size,
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dmem_data_size => dmem_data_size,
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dmem_read_req => dmem_read_req,
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dmem_read_req => dmem_read_req,
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dmem_write_req => dmem_write_req,
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dmem_read_ack => dmem_read_ack,
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dmem_read_ack => dmem_read_ack,
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dmem_write_req => dmem_write_req,
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dmem_write_ack => dmem_write_ack,
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dmem_write_ack => dmem_write_ack,
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wb_inputs => dmem_if_inputs,
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wb_outputs => dmem_if_outputs
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);
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arbiter: entity work.pp_wb_arbiter
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port map(
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clk => clk,
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reset => reset,
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--m1_inputs => dmem_if_inputs,
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--m1_outputs => dmem_if_outputs,
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m1_inputs => icache_inputs,
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m1_outputs => icache_outputs,
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m2_inputs => dmem_if_inputs,
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m2_outputs => dmem_if_outputs,
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wb_adr_out => wb_adr_out,
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wb_adr_out => wb_adr_out,
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wb_sel_out => wb_sel_out,
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wb_sel_out => wb_sel_out,
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wb_cyc_out => wb_cyc_out,
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wb_cyc_out => wb_cyc_out,
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wb_stb_out => wb_stb_out,
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wb_stb_out => wb_stb_out,
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wb_we_out => wb_we_out,
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wb_we_out => wb_we_out,
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