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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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use ieee.std_logic_1164.all;
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use work.pp_types.all;
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--! @brief Simple priority-based wishbone arbiter.
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--! This module is used as an arbiter between the instruction and data caches.
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entity pp_wb_arbiter is
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port(
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clk : in std_logic;
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reset : in std_logic;
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-- Wishbone input 1:
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m1_inputs : out wishbone_master_inputs;
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m1_outputs : in wishbone_master_outputs;
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-- Wishbone input 2:
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m2_inputs : out wishbone_master_inputs;
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m2_outputs : in wishbone_master_outputs;
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-- Wishbone interface:
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wb_adr_out : out std_logic_vector(31 downto 0);
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wb_sel_out : out std_logic_vector( 3 downto 0);
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wb_cyc_out : out std_logic;
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wb_stb_out : out std_logic;
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wb_we_out : out std_logic;
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wb_dat_out : out std_logic_vector(31 downto 0);
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wb_dat_in : in std_logic_vector(31 downto 0);
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wb_ack_in : in std_logic
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);
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end entity pp_wb_arbiter;
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architecture behaviour of pp_wb_arbiter is
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type state_type is (IDLE, M1_BUSY, M2_BUSY);
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signal state : state_type := IDLE;
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begin
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m1_inputs <= (ack => wb_ack_in, dat => wb_dat_in) when state = M1_BUSY else (ack => '0', dat => (others => '0'));
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m2_inputs <= (ack => wb_ack_in, dat => wb_dat_in) when state = M2_BUSY else (ack => '0', dat => (others => '0'));
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output_mux: process(state, m1_outputs, m2_outputs)
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begin
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case state is
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when IDLE =>
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wb_adr_out <= (others => '0');
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wb_sel_out <= (others => '0');
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wb_dat_out <= (others => '0');
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wb_cyc_out <= '0';
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wb_stb_out <= '0';
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wb_we_out <= '0';
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when M1_BUSY =>
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wb_adr_out <= m1_outputs.adr;
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wb_sel_out <= m1_outputs.sel;
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wb_dat_out <= m1_outputs.dat;
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wb_cyc_out <= m1_outputs.cyc;
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wb_stb_out <= m1_outputs.stb;
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wb_we_out <= m1_outputs.we;
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when M2_BUSY =>
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wb_adr_out <= m2_outputs.adr;
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wb_sel_out <= m2_outputs.sel;
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wb_dat_out <= m2_outputs.dat;
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wb_cyc_out <= m2_outputs.cyc;
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wb_stb_out <= m2_outputs.stb;
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wb_we_out <= m2_outputs.we;
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end case;
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end process output_mux;
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controller: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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state <= IDLE;
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else
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case state is
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when IDLE =>
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if m1_outputs.cyc = '1' then
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state <= M1_BUSY;
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elsif m2_outputs.cyc = '1' then
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state <= M2_BUSY;
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end if;
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when M1_BUSY =>
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if m1_outputs.cyc = '0' then
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state <= IDLE;
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end if;
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when M2_BUSY =>
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if m2_outputs.cyc = '0' then
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state <= IDLE;
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end if;
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end case;
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end if;
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end if;
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end process controller;
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end architecture behaviour;
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