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Line 10... |
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use work.pp_constants.all;
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use work.pp_constants.all;
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entity tb_processor is
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entity tb_processor is
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generic(
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generic(
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IMEM_SIZE : natural := 2048; --! Size of the instruction memory in bytes.
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IMEM_SIZE : natural := 4096; --! Size of the instruction memory in bytes.
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DMEM_SIZE : natural := 2048; --! Size of the data memory in bytes.
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DMEM_SIZE : natural := 4096; --! Size of the data memory in bytes.
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RESET_ADDRESS : std_logic_vector := x"00000200"; --! Processor reset address
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IMEM_START_ADDR : std_logic_vector := x"00000100"; --! Instruction memory start address
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IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
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IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
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DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
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DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
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);
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);
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end entity tb_processor;
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end entity tb_processor;
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architecture testbench of tb_processor is
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architecture testbench of tb_processor is
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-- Processor component prototype:
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component pp_core is
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port(
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-- Common inputs:
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clk : in std_logic; --! Processor clock
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reset : in std_logic; --! Reset signal
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timer_clk : in std_logic; --! Timer clock input
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-- Instruction memory interface:
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imem_address : out std_logic_vector(31 downto 0); --! Address of the next instruction
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imem_data_in : in std_logic_vector(31 downto 0); --! Instruction input
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imem_req : out std_logic;
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imem_ack : in std_logic;
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-- Data memory interface:
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dmem_address : out std_logic_vector(31 downto 0); --! Data address
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dmem_data_in : in std_logic_vector(31 downto 0); --! Input from the data memory
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dmem_data_out : out std_logic_vector(31 downto 0); --! Ouptut to the data memory
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dmem_data_size : out std_logic_vector( 1 downto 0); --! Size of the data, 1 = 8 bits, 2 = 16 bits, 0 = 32 bits.
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dmem_read_req : out std_logic; --! Data memory read request
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dmem_read_ack : in std_logic; --! Data memory read acknowledge
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dmem_write_req : out std_logic; --! Data memory write request
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dmem_write_ack : in std_logic; --! Data memory write acknowledge
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-- Tohost/fromhost interface:
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fromhost_data : in std_logic_vector(31 downto 0); --! Data from the host/simulator.
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fromhost_write_en : in std_logic; --! Write enable signal from the host/simulator.
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tohost_data : out std_logic_vector(31 downto 0); --! Data to the host/simulator.
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tohost_write_en : out std_logic; --! Write enable signal to the host/simulator.
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-- External interrupt input:
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irq : in std_logic_vector(7 downto 0) --! IRQ input
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);
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end component pp_core;
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-- Clock signal:
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-- Clock signal:
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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-- Timer clock signal:
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signal timer_clk : std_logic := '0';
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constant timer_clk_period : time := 100 ns;
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-- Common inputs:
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-- Common inputs:
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signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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-- Instruction memory interface:
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-- Instruction memory interface:
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signal imem_address : std_logic_vector(31 downto 0);
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signal imem_address : std_logic_vector(31 downto 0);
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Line 61... |
signal imem_initialized, dmem_initialized, initialized : boolean := false;
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signal imem_initialized, dmem_initialized, initialized : boolean := false;
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-- Memory array type:
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-- Memory array type:
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type memory_array is array(natural range <>) of std_logic_vector(7 downto 0);
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type memory_array is array(natural range <>) of std_logic_vector(7 downto 0);
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constant IMEM_BASE : natural := 0;
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constant IMEM_BASE : natural := 0;
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constant IMEM_END : natural := IMEM_SIZE - 1;
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constant IMEM_END : natural := IMEM_BASE + IMEM_SIZE - 1;
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constant DMEM_BASE : natural := IMEM_SIZE;
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constant DMEM_BASE : natural := IMEM_END + 1;
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constant DMEM_END : natural := IMEM_SIZE + DMEM_SIZE - 1;
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constant DMEM_END : natural := IMEM_END + DMEM_SIZE;
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-- Memories:
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-- Memories:
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signal imem_memory : memory_array(IMEM_BASE to IMEM_END);
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signal imem_memory : memory_array(IMEM_BASE to IMEM_END);
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signal dmem_memory : memory_array(DMEM_BASE to DMEM_END);
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signal dmem_memory : memory_array(DMEM_BASE to DMEM_END);
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signal simulation_finished : boolean := false;
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signal simulation_finished : boolean := false;
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begin
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begin
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uut: pp_core
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uut: entity work.pp_core
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port map(
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generic map(
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RESET_ADDRESS => RESET_ADDRESS
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) port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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timer_clk => clk,
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timer_clk => timer_clk,
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imem_address => imem_address,
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imem_address => imem_address,
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imem_data_in => imem_data_in,
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imem_data_in => imem_data_in,
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imem_req => imem_req,
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imem_req => imem_req,
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imem_ack => imem_ack,
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imem_ack => imem_ack,
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dmem_address => dmem_address,
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dmem_address => dmem_address,
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| Line 138... |
Line 111... |
if simulation_finished then
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if simulation_finished then
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wait;
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wait;
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end if;
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end if;
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end process clock;
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end process clock;
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timer_clock: process
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begin
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timer_clk <= '0';
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wait for timer_clk_period / 2;
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timer_clk <= '1';
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wait for timer_clk_period / 2;
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if simulation_finished then
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wait;
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end if;
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end process timer_clock;
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--! Initializes the instruction memory from file.
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--! Initializes the instruction memory from file.
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imem_init: process
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imem_init: process
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file imem_file : text open READ_MODE is IMEM_FILENAME;
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file imem_file : text open READ_MODE is IMEM_FILENAME;
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variable input_line : line;
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variable input_line : line;
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variable input_index : natural;
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variable input_index : natural;
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variable input_value : std_logic_vector(31 downto 0);
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variable input_value : std_logic_vector(31 downto 0);
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begin
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begin
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for i in IMEM_BASE / 4 to IMEM_END / 4 loop
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for i in to_integer(unsigned(IMEM_START_ADDR)) / 4 to IMEM_END / 4 loop
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--for i in IMEM_BASE / 4 to IMEM_END / 4 loop
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if not endfile(imem_file) then
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if not endfile(imem_file) then
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readline(imem_file, input_line);
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readline(imem_file, input_line);
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hread(input_line, input_value);
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hread(input_line, input_value);
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imem_memory(i * 4 + 0) <= input_value( 7 downto 0);
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imem_memory(i * 4 + 0) <= input_value( 7 downto 0);
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imem_memory(i * 4 + 1) <= input_value(15 downto 8);
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imem_memory(i * 4 + 1) <= input_value(15 downto 8);
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| Line 209... |
Line 195... |
when b"01" => -- 8 bits
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when b"01" => -- 8 bits
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dmem_memory(to_integer(unsigned(dmem_address))) <= dmem_data_out(7 downto 0);
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dmem_memory(to_integer(unsigned(dmem_address))) <= dmem_data_out(7 downto 0);
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when b"10" => -- 16 bits
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when b"10" => -- 16 bits
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dmem_memory(to_integer(unsigned(dmem_address)) + 0) <= dmem_data_out( 7 downto 0);
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dmem_memory(to_integer(unsigned(dmem_address)) + 0) <= dmem_data_out( 7 downto 0);
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dmem_memory(to_integer(unsigned(dmem_address)) + 1) <= dmem_data_out(15 downto 8);
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dmem_memory(to_integer(unsigned(dmem_address)) + 1) <= dmem_data_out(15 downto 8);
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when others => -- Reserved for possible future 64 bit support
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when others =>
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end case;
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end case;
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dmem_write_ack <= '1';
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dmem_write_ack <= '1';
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end if;
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end if;
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end if;
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end if;
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end process dmem_init_and_write;
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end process dmem_init_and_write;
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| Line 257... |
Line 243... |
when b"10" => -- 16 bits
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when b"10" => -- 16 bits
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dmem_data_in(15 downto 8) <= dmem_memory(to_integer(unsigned(dmem_address)) + 1);
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dmem_data_in(15 downto 8) <= dmem_memory(to_integer(unsigned(dmem_address)) + 1);
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dmem_data_in( 7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)) + 0);
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dmem_data_in( 7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)) + 0);
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when b"01" => -- 8 bits
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when b"01" => -- 8 bits
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dmem_data_in(7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)));
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dmem_data_in(7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)));
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when others => -- Reserved for possible future 64 bit support
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when others =>
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end case;
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end case;
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dmem_read_ack <= '1';
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dmem_read_ack <= '1';
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end if;
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end if;
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end if;
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end if;
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end process dmem_read;
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end process dmem_read;
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