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[/] [potato/] [trunk/] [testbenches/] [tb_processor.vhd] - Diff between revs 3 and 58

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use work.pp_constants.all;
use work.pp_constants.all;
 
 
entity tb_processor is
entity tb_processor is
        generic(
        generic(
                IMEM_SIZE : natural := 2048; --! Size of the instruction memory in bytes.
                IMEM_SIZE : natural := 4096; --! Size of the instruction memory in bytes.
                DMEM_SIZE : natural := 2048; --! Size of the data memory in bytes.
                DMEM_SIZE : natural := 4096; --! Size of the data memory in bytes.
 
                RESET_ADDRESS   : std_logic_vector := x"00000200"; --! Processor reset address
 
                IMEM_START_ADDR : std_logic_vector := x"00000100"; --! Instruction memory start address
                IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
                IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
                DMEM_FILENAME : string := "dmem_testfile.hex"  --! File containing the contents of data memory.
                DMEM_FILENAME : string := "dmem_testfile.hex"  --! File containing the contents of data memory.
        );
        );
end entity tb_processor;
end entity tb_processor;
 
 
architecture testbench of tb_processor is
architecture testbench of tb_processor is
 
 
        -- Processor component prototype:
 
        component pp_core is
 
                port(
 
                        -- Common inputs:
 
                        clk       : in std_logic; --! Processor clock
 
                        reset     : in std_logic; --! Reset signal
 
                        timer_clk : in std_logic; --! Timer clock input
 
 
 
                        -- Instruction memory interface:
 
                        imem_address : out std_logic_vector(31 downto 0); --! Address of the next instruction
 
                        imem_data_in : in  std_logic_vector(31 downto 0); --! Instruction input
 
                        imem_req     : out std_logic;
 
                        imem_ack     : in  std_logic;
 
 
 
                        -- Data memory interface:
 
                        dmem_address   : out std_logic_vector(31 downto 0); --! Data address
 
                        dmem_data_in   : in  std_logic_vector(31 downto 0); --! Input from the data memory
 
                        dmem_data_out  : out std_logic_vector(31 downto 0); --! Ouptut to the data memory
 
                        dmem_data_size : out std_logic_vector( 1 downto 0);  --! Size of the data, 1 = 8 bits, 2 = 16 bits, 0 = 32 bits. 
 
                        dmem_read_req  : out std_logic; --! Data memory read request
 
                        dmem_read_ack  : in  std_logic; --! Data memory read acknowledge
 
                        dmem_write_req : out std_logic; --! Data memory write request
 
                        dmem_write_ack : in  std_logic; --! Data memory write acknowledge
 
 
 
                        -- Tohost/fromhost interface:
 
                        fromhost_data     : in  std_logic_vector(31 downto 0); --! Data from the host/simulator.
 
                        fromhost_write_en : in  std_logic;                     --! Write enable signal from the host/simulator.
 
                        tohost_data       : out std_logic_vector(31 downto 0); --! Data to the host/simulator.
 
                        tohost_write_en   : out std_logic;                     --! Write enable signal to the host/simulator.
 
 
 
                        -- External interrupt input:
 
                        irq : in std_logic_vector(7 downto 0) --! IRQ input
 
                );
 
        end component pp_core;
 
 
 
        -- Clock signal:
        -- Clock signal:
        signal clk : std_logic := '0';
        signal clk : std_logic := '0';
        constant clk_period : time := 10 ns;
        constant clk_period : time := 10 ns;
 
 
 
        -- Timer clock signal:
 
        signal timer_clk : std_logic := '0';
 
        constant timer_clk_period : time := 100 ns;
 
 
        -- Common inputs:
        -- Common inputs:
        signal reset  : std_logic := '1';
        signal reset  : std_logic := '1';
 
 
        -- Instruction memory interface:
        -- Instruction memory interface:
        signal imem_address : std_logic_vector(31 downto 0);
        signal imem_address : std_logic_vector(31 downto 0);
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        signal imem_initialized, dmem_initialized, initialized : boolean := false;
        signal imem_initialized, dmem_initialized, initialized : boolean := false;
 
 
        -- Memory array type:
        -- Memory array type:
        type memory_array is array(natural range <>) of std_logic_vector(7 downto 0);
        type memory_array is array(natural range <>) of std_logic_vector(7 downto 0);
        constant IMEM_BASE : natural := 0;
        constant IMEM_BASE : natural := 0;
        constant IMEM_END  : natural := IMEM_SIZE - 1;
        constant IMEM_END  : natural := IMEM_BASE + IMEM_SIZE - 1;
        constant DMEM_BASE : natural := IMEM_SIZE;
        constant DMEM_BASE : natural := IMEM_END + 1;
        constant DMEM_END  : natural := IMEM_SIZE + DMEM_SIZE - 1;
        constant DMEM_END  : natural := IMEM_END + DMEM_SIZE;
 
 
        -- Memories:
        -- Memories:
        signal imem_memory : memory_array(IMEM_BASE to IMEM_END);
        signal imem_memory : memory_array(IMEM_BASE to IMEM_END);
        signal dmem_memory : memory_array(DMEM_BASE to DMEM_END);
        signal dmem_memory : memory_array(DMEM_BASE to DMEM_END);
 
 
        signal simulation_finished : boolean := false;
        signal simulation_finished : boolean := false;
 
 
begin
begin
 
 
        uut: pp_core
        uut: entity work.pp_core
                port map(
                generic map(
 
                        RESET_ADDRESS => RESET_ADDRESS
 
                ) port map(
                        clk => clk,
                        clk => clk,
                        reset => reset,
                        reset => reset,
                        timer_clk => clk,
                        timer_clk => timer_clk,
                        imem_address => imem_address,
                        imem_address => imem_address,
                        imem_data_in => imem_data_in,
                        imem_data_in => imem_data_in,
                        imem_req => imem_req,
                        imem_req => imem_req,
                        imem_ack => imem_ack,
                        imem_ack => imem_ack,
                        dmem_address => dmem_address,
                        dmem_address => dmem_address,
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                if simulation_finished then
                if simulation_finished then
                        wait;
                        wait;
                end if;
                end if;
        end process clock;
        end process clock;
 
 
 
        timer_clock: process
 
        begin
 
                timer_clk <= '0';
 
                wait for timer_clk_period / 2;
 
                timer_clk <= '1';
 
                wait for timer_clk_period / 2;
 
 
 
                if simulation_finished then
 
                        wait;
 
                end if;
 
        end process timer_clock;
 
 
        --! Initializes the instruction memory from file.
        --! Initializes the instruction memory from file.
        imem_init: process
        imem_init: process
                file imem_file : text open READ_MODE is IMEM_FILENAME;
                file imem_file : text open READ_MODE is IMEM_FILENAME;
                variable input_line  : line;
                variable input_line  : line;
                variable input_index : natural;
                variable input_index : natural;
                variable input_value : std_logic_vector(31 downto 0);
                variable input_value : std_logic_vector(31 downto 0);
        begin
        begin
                for i in IMEM_BASE / 4 to IMEM_END / 4 loop
                for i in to_integer(unsigned(IMEM_START_ADDR)) / 4 to IMEM_END / 4 loop
 
                --for i in IMEM_BASE / 4 to IMEM_END / 4 loop
                        if not endfile(imem_file) then
                        if not endfile(imem_file) then
                                readline(imem_file, input_line);
                                readline(imem_file, input_line);
                                hread(input_line, input_value);
                                hread(input_line, input_value);
                                imem_memory(i * 4 + 0) <= input_value( 7 downto  0);
                                imem_memory(i * 4 + 0) <= input_value( 7 downto  0);
                                imem_memory(i * 4 + 1) <= input_value(15 downto  8);
                                imem_memory(i * 4 + 1) <= input_value(15 downto  8);
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                                        when b"01" => -- 8 bits
                                        when b"01" => -- 8 bits
                                                dmem_memory(to_integer(unsigned(dmem_address))) <= dmem_data_out(7 downto 0);
                                                dmem_memory(to_integer(unsigned(dmem_address))) <= dmem_data_out(7 downto 0);
                                        when b"10" => -- 16 bits
                                        when b"10" => -- 16 bits
                                                dmem_memory(to_integer(unsigned(dmem_address)) + 0) <= dmem_data_out( 7 downto 0);
                                                dmem_memory(to_integer(unsigned(dmem_address)) + 0) <= dmem_data_out( 7 downto 0);
                                                dmem_memory(to_integer(unsigned(dmem_address)) + 1) <= dmem_data_out(15 downto 8);
                                                dmem_memory(to_integer(unsigned(dmem_address)) + 1) <= dmem_data_out(15 downto 8);
                                        when others => -- Reserved for possible future 64 bit support
                                        when others =>
                                end case;
                                end case;
                                dmem_write_ack <= '1';
                                dmem_write_ack <= '1';
                        end if;
                        end if;
                end if;
                end if;
        end process dmem_init_and_write;
        end process dmem_init_and_write;
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                                        when b"10" => -- 16 bits
                                        when b"10" => -- 16 bits
                                                dmem_data_in(15 downto 8) <= dmem_memory(to_integer(unsigned(dmem_address)) + 1);
                                                dmem_data_in(15 downto 8) <= dmem_memory(to_integer(unsigned(dmem_address)) + 1);
                                                dmem_data_in( 7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)) + 0);
                                                dmem_data_in( 7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)) + 0);
                                        when b"01" => -- 8  bits
                                        when b"01" => -- 8  bits
                                                dmem_data_in(7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)));
                                                dmem_data_in(7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)));
                                        when others => -- Reserved for possible future 64 bit support
                                        when others =>
                                end case;
                                end case;
                                dmem_read_ack <= '1';
                                dmem_read_ack <= '1';
                        end if;
                        end if;
                end if;
                end if;
        end process dmem_read;
        end process dmem_read;

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