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use work.pp_utilities.all;
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use work.pp_utilities.all;
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--! @brief Testbench providing a full SoC architecture connected with a Wishbone bus.
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--! @brief Testbench providing a full SoC architecture connected with a Wishbone bus.
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entity tb_soc is
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entity tb_soc is
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generic(
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generic(
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IMEM_SIZE : natural := 2048; --! Size of the instruction memory in bytes.
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IMEM_SIZE : natural := 4096; --! Size of the instruction memory in bytes.
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DMEM_SIZE : natural := 2048; --! Size of the data memory in bytes.
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DMEM_SIZE : natural := 4096; --! Size of the data memory in bytes.
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RESET_ADDRESS : std_logic_vector := x"00000200"; --! Processor reset address
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IMEM_START_ADDR : std_logic_vector := x"00000100"; --! Instruction memory start address
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IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
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IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
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DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
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DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
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);
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);
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end entity tb_soc;
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end entity tb_soc;
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Line 27... |
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-- Clock signals:
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-- Clock signals:
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signal clk : std_logic;
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signal clk : std_logic;
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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signal timer_clk : std_logic;
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constant timer_clk_period : time := 100 ns;
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-- Reset:
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-- Reset:
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signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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-- Interrupts:
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-- Interrupts:
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signal irq : std_logic_vector(7 downto 0) := (others => '0');
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signal irq : std_logic_vector(7 downto 0) := (others => '0');
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Line 96... |
signal simulation_finished : boolean := false;
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signal simulation_finished : boolean := false;
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begin
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begin
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processor: entity work.pp_potato
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processor: entity work.pp_potato
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port map(
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generic map(
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RESET_ADDRESS => RESET_ADDRESS
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) port map(
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clk => clk,
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clk => clk,
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reset => processor_reset,
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reset => processor_reset,
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timer_clk => timer_clk,
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irq => irq,
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irq => irq,
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fromhost_data => fromhost_data,
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fromhost_data => fromhost_data,
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fromhost_updated => fromhost_updated,
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fromhost_updated => fromhost_updated,
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tohost_data => tohost_data,
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tohost_data => tohost_data,
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tohost_updated => tohost_updated,
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tohost_updated => tohost_updated,
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Line 206... |
variable input_line : line;
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variable input_line : line;
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variable input_index : natural;
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variable input_index : natural;
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variable input_value : std_logic_vector(31 downto 0);
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variable input_value : std_logic_vector(31 downto 0);
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variable temp : std_logic_vector(31 downto 0);
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variable temp : std_logic_vector(31 downto 0);
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constant DMEM_START : natural := IMEM_SIZE;
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constant DMEM_START_ADDR : natural := IMEM_SIZE;
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begin
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begin
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if not initialized then
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if not initialized then
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-- Read the instruction memory file:
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-- Read the instruction memory file:
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for i in 0 to IMEM_SIZE loop
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for i in 0 to (IMEM_SIZE / 4) - 1 loop
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exit when endfile(imem_file);
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exit when endfile(imem_file);
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readline(imem_file, input_line);
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readline(imem_file, input_line);
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hread(input_line, input_value);
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hread(input_line, input_value);
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init_adr_out <= std_logic_vector(to_unsigned(i * 4, init_adr_out'length));
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init_adr_out <= std_logic_vector(to_unsigned(to_integer(unsigned(IMEM_START_ADDR)) + (i * 4),
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init_adr_out'length));
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init_dat_out <= input_value;
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init_dat_out <= input_value;
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init_cyc_out <= '1';
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init_cyc_out <= '1';
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init_stb_out <= '1';
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init_stb_out <= '1';
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wait until imem_ack_out = '1';
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wait until imem_ack_out = '1';
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wait for clk_period;
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wait for clk_period;
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Line 233... |
init_cyc_out <= '0';
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init_cyc_out <= '0';
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init_stb_out <= '0';
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init_stb_out <= '0';
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wait for clk_period;
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wait for clk_period;
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-- Read the data memory file:
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-- Read the data memory file:
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for i in 0 to DMEM_SIZE loop
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for i in 0 to (DMEM_SIZE / 4) - 1 loop
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exit when endfile(dmem_file);
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exit when endfile(dmem_file);
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readline(dmem_file, input_line);
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readline(dmem_file, input_line);
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hread(input_line, input_value);
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hread(input_line, input_value);
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-- Swap endianness, TODO: prevent this, fix scripts/extract_hex.sh
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-- Swap endianness, TODO: prevent this, fix scripts/extract_hex.sh
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temp(7 downto 0) := input_value(31 downto 24);
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temp(7 downto 0) := input_value(31 downto 24);
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temp(15 downto 8) := input_value(23 downto 16);
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temp(15 downto 8) := input_value(23 downto 16);
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temp(23 downto 16) := input_value(15 downto 8);
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temp(23 downto 16) := input_value(15 downto 8);
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temp(31 downto 24) := input_value(7 downto 0);
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temp(31 downto 24) := input_value(7 downto 0);
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input_value := temp;
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input_value := temp;
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init_adr_out <= std_logic_vector(to_unsigned(DMEM_START + (i * 4), init_adr_out'length));
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init_adr_out <= std_logic_vector(to_unsigned(DMEM_START_ADDR + (i * 4), init_adr_out'length));
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init_dat_out <= input_value;
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init_dat_out <= input_value;
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init_cyc_out <= '1';
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init_cyc_out <= '1';
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init_stb_out <= '1';
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init_stb_out <= '1';
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wait until dmem_ack_out = '1';
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wait until dmem_ack_out = '1';
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wait for clk_period;
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wait for clk_period;
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Line 279... |
if simulation_finished then
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if simulation_finished then
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wait;
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wait;
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end if;
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end if;
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end process clock;
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end process clock;
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timer_clock: process
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begin
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timer_clk <= '1';
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wait for timer_clk_period / 2;
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timer_clk <= '0';
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wait for timer_clk_period / 2;
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if simulation_finished then
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wait;
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end if;
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end process timer_clock;
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stimulus: process
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stimulus: process
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begin
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begin
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wait for clk_period * 2;
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wait for clk_period * 2;
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reset <= '0';
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reset <= '0';
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