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[/] [potato/] [trunk/] [tests/] [timer.S] - Diff between revs 51 and 58
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# The Potato Processor - A simple RISC-V based processor for FPGAs
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# (c) Kristian Klomsten Skordal 2014 - 2015
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# Report bugs and issues on
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# Simplified timer interrupt test.
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#include "riscv_test.h"
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#include "test_macros.h"
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#define TIMER_DELTA_T 10
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#define MIE_STIE MIP_STIP
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RVTEST_RV32M
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RVTEST_CODE_BEGIN
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li s8, 0 # Number of timer interrupts taken
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li s9, 10 # Number of timer interrupts to wait for
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# Set the time of the next timer interrupt:
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csrr a0, mtime
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addi a0, a0, TIMER_DELTA_T
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csrw mtimecmp, a0
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# Enable the timer interrupt:
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li a0, (1 << 7)
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csrs mie, a0
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csrs mstatus, MSTATUS_IE
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wait_for_count:
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# TODO: wfi not yet supported
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j wait_for_count
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mtvec_handler:
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li t0, (1 << 31) + 1 # Interrupt bit set + timer interrupt exception code
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csrr t1, mcause
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bne t0, t1, fail # Fail if not timer interrupt
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addi s8, s8, 1
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beq s8, s9, pass # Pass the test if the correct number of interrupts have been taken
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# Reset the timer:
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csrr a0, mtime
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addi a0, a0, TIMER_DELTA_T
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csrw mtimecmp, a0
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eret
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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